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authorAli Saidi <saidi@eecs.umich.edu>2007-09-28 13:21:30 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-09-28 13:21:30 -0400
commit887cd6a273f8777580fc3a046090c6b5244e9cad (patch)
tree8f053cad51065661938a4e12f7d82ebac4b4cfc8 /src/cpu
parent58c448ced510835631527fa64a0ebd0b497b525b (diff)
downloadgem5-887cd6a273f8777580fc3a046090c6b5244e9cad.tar.xz
Update statistics to use cycles properly instead of ticks
--HG-- extra : convert_revision : 62911280b631ef24720f9ce701d1c19a9b8a9784
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/base.hh1
-rw-r--r--src/cpu/o3/cpu.cc3
-rw-r--r--src/cpu/simple/timing.cc8
3 files changed, 7 insertions, 5 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 76f6e4684..6f4158d47 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -84,6 +84,7 @@ class BaseCPU : public MemObject
inline Tick frequency() const { return Clock::Frequency / clock; }
inline Tick cycles(int numCycles) const { return clock * numCycles; }
inline Tick curCycle() const { return curTick / clock; }
+ inline Tick tickToCycles(Tick val) const { return val / clock; }
// @todo remove me after debugging with legion done
Tick instCount() { return instCnt; }
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 98e200944..b2b7e09c0 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1409,7 +1409,8 @@ FullO3CPU<Impl>::wakeCPU()
DPRINTF(Activity, "Waking up CPU\n");
- idleCycles += (curTick - 1) - lastRunningCycle;
+ idleCycles += tickToCycles((curTick - 1) - lastRunningCycle);
+ numCycles += tickToCycles((curTick - 1) - lastRunningCycle);
tickEvent.schedule(nextCycle());
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 8d1cf9a17..eee5b8cb5 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -180,7 +180,7 @@ TimingSimpleCPU::switchOut()
{
assert(status() == Running || status() == Idle);
_status = SwitchedOut;
- numCycles += curTick - previousTick;
+ numCycles += tickToCycles(curTick - previousTick);
// If we've been scheduled to resume but are then told to switch out,
// we'll need to cancel it.
@@ -483,7 +483,7 @@ TimingSimpleCPU::fetch()
advanceInst(fault);
}
- numCycles += curTick - previousTick;
+ numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
}
@@ -512,7 +512,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
_status = Running;
- numCycles += curTick - previousTick;
+ numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
if (getState() == SimObject::Draining) {
@@ -629,7 +629,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
assert(_status == DcacheWaitResponse);
_status = Running;
- numCycles += curTick - previousTick;
+ numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);