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author | Kevin Lim <ktlim@umich.edu> | 2006-10-09 22:49:58 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-10-09 22:49:58 -0400 |
commit | a9ae6c8656dc233996c81cdeb6f5c8539442af95 (patch) | |
tree | 5c736df32db9626cc57051983725653a32813c68 /src/cpu | |
parent | 92bf23bed62bd8f1e85d1da0506b6e1b71b27d15 (diff) | |
download | gem5-a9ae6c8656dc233996c81cdeb6f5c8539442af95.tar.xz |
Comment out code that messed up SMT (but will be needed eventually).
src/cpu/o3/cpu.cc:
Comment out reseting CPU structures for now. This can be updated to work in the future.
--HG--
extra : convert_revision : bc1a86e2fe47da5acb14ba8b64568b0355431f1c
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/o3/cpu.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index d1d25dd7f..4c9a8e91f 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -701,10 +701,17 @@ FullO3CPU<Impl>::removeThread(unsigned tid) assert(iew.ldstQueue.getCount(tid) == 0); // Reset ROB/IQ/LSQ Entries + + // Commented out for now. This should be possible to do by + // telling all the pipeline stages to drain first, and then + // checking until the drain completes. Once the pipeline is + // drained, call resetEntries(). - 10-09-06 ktlim +/* if (activeThreads.size() >= 1) { commit.rob->resetEntries(); iew.resetEntries(); } +*/ } |