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authorAndreas Hansson <andreas.hansson@arm.com>2012-04-06 13:46:31 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-04-06 13:46:31 -0400
commitb00949d88bb3185dfa2e27799de7f90e5a449be8 (patch)
tree74789b938463bcf38d5ffd5e6be5ef7a02d84a58 /src/cpu
parentdbe1608fd58d818f59a0adf5f3fb562f61242f99 (diff)
downloadgem5-b00949d88bb3185dfa2e27799de7f90e5a449be8.tar.xz
MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. --HG-- rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py rename : src/mem/physical.cc => src/mem/abstract_mem.cc rename : src/mem/physical.hh => src/mem/abstract_mem.hh rename : src/mem/physical.cc => src/mem/simple_mem.cc rename : src/mem/physical.hh => src/mem/simple_mem.hh
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/checker/thread_context.hh2
-rw-r--r--src/cpu/inorder/thread_context.hh4
-rw-r--r--src/cpu/o3/fetch_impl.hh3
-rw-r--r--src/cpu/ozone/cpu.hh4
-rw-r--r--src/cpu/simple/atomic.cc17
-rw-r--r--src/cpu/simple/atomic.hh2
6 files changed, 7 insertions, 25 deletions
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 4aed0501c..710d827cc 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -121,8 +121,6 @@ class CheckerThreadContext : public ThreadContext
System *getSystemPtr() { return actualTC->getSystemPtr(); }
- PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
-
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index aaf7d6ede..6f9bc5dac 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -114,10 +114,6 @@ class InOrderThreadContext : public ThreadContext
void setNextMicroPC(uint64_t val) { };
- /** Returns a pointer to physical memory. */
- PhysicalMemory *getPhysMemPtr()
- { assert(0); return 0; /*return cpu->physmem;*/ }
-
/** Returns a pointer to this thread's kernel statistics. */
TheISA::Kernel::Statistics *getKernelStats()
{ return thread->kernelStats; }
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index df6ab26d5..0ff515855 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -60,7 +60,6 @@
#include "debug/Activity.hh"
#include "debug/Fetch.hh"
#include "mem/packet.hh"
-#include "mem/request.hh"
#include "params/DerivO3CPU.hh"
#include "sim/byteswap.hh"
#include "sim/core.hh"
@@ -602,7 +601,7 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
// Check that we're not going off into random memory
// If we have, just wait around for commit to squash something and put
// us on the right track
- if (!cpu->system->isMemory(mem_req->getPaddr())) {
+ if (!cpu->system->isMemAddr(mem_req->getPaddr())) {
warn("Address %#x is outside of physical memory, stopping fetch\n",
mem_req->getPaddr());
fetchStatus[tid] = NoGoodAddr;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 1bd2ee25b..91de37eff 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -60,7 +60,6 @@ class Checkpoint;
class EndQuiesceEvent;
class MemoryController;
class MemObject;
-class PhysicalMemory;
class Process;
class Request;
@@ -107,8 +106,6 @@ class OzoneCPU : public BaseCPU
System *getSystemPtr() { return cpu->system; }
- PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
-
TheISA::Kernel::Statistics *getKernelStats()
{ return thread->getKernelStats(); }
@@ -314,7 +311,6 @@ class OzoneCPU : public BaseCPU
TheISA::TLB *itb;
TheISA::TLB *dtb;
System *system;
- PhysicalMemory *physmem;
FrontEnd *frontEnd;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 41bcf9268..90f4fa579 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -95,10 +95,6 @@ AtomicSimpleCPU::init()
}
}
- if (fastmem) {
- AddrRangeList pmAddrList = system->physmem->getAddrRanges();
- physMemAddr = *pmAddrList.begin();
- }
// Atomic doesn't do MT right now, so contextId == threadId
ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
@@ -283,8 +279,8 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
if (req->isMmappedIpr())
dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
else {
- if (fastmem && pkt.getAddr() == physMemAddr)
- dcache_latency += system->physmem->doAtomicAccess(&pkt);
+ if (fastmem && system->isMemAddr(pkt.getAddr()))
+ system->getPhysMem().access(&pkt);
else
dcache_latency += dcachePort.sendAtomic(&pkt);
}
@@ -385,8 +381,8 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
dcache_latency +=
TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
- if (fastmem && pkt.getAddr() == physMemAddr)
- dcache_latency += system->physmem->doAtomicAccess(&pkt);
+ if (fastmem && system->isMemAddr(pkt.getAddr()))
+ system->getPhysMem().access(&pkt);
else
dcache_latency += dcachePort.sendAtomic(&pkt);
}
@@ -481,9 +477,8 @@ AtomicSimpleCPU::tick()
Packet::Broadcast);
ifetch_pkt.dataStatic(&inst);
- if (fastmem && ifetch_pkt.getAddr() == physMemAddr)
- icache_latency =
- system->physmem->doAtomicAccess(&ifetch_pkt);
+ if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
+ system->getPhysMem().access(&ifetch_pkt);
else
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index c0112836a..3e6238f7d 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -110,8 +110,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU
bool dcache_access;
Tick dcache_latency;
- Range<Addr> physMemAddr;
-
protected:
/** Return a reference to the data port. */