mips: cleanup ISA-specific code

***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
 anyway.

4 files changed, 0 insertions, 74 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 9786283a2..bf7577cc7 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -199,59 +199,3 @@ class BaseCPU(MemObject):
         self.l2cache = l2c
         self.l2cache.cpu_side = self.toL2Bus.port
         self._cached_ports = ['l2cache.mem_side']
-
-    if buildEnv['TARGET_ISA'] == 'mips':
-        CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
-        CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
-        CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
-        CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
-        CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
-        CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
-        CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
-        CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
-        CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
-        CP0_Config_AT = Param.Unsigned(0,"No Description")
-        CP0_Config_AR = Param.Unsigned(0,"No Description")
-        CP0_Config_MT = Param.Unsigned(0,"No Description")
-        CP0_Config_VI = Param.Unsigned(0,"No Description")
-        CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
-        CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
-        CP0_Config1_IS = Param.Unsigned(0,"No Description")
-        CP0_Config1_IL = Param.Unsigned(0,"No Description")
-        CP0_Config1_IA = Param.Unsigned(0,"No Description")
-        CP0_Config1_DS = Param.Unsigned(0,"No Description")
-        CP0_Config1_DL = Param.Unsigned(0,"No Description")
-        CP0_Config1_DA = Param.Unsigned(0,"No Description")
-        CP0_Config1_C2 = Param.Bool(False,"No Description")
-        CP0_Config1_MD = Param.Bool(False,"No Description")
-        CP0_Config1_PC = Param.Bool(False,"No Description")
-        CP0_Config1_WR = Param.Bool(False,"No Description")
-        CP0_Config1_CA = Param.Bool(False,"No Description")
-        CP0_Config1_EP = Param.Bool(False,"No Description")
-        CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
-        CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
-        CP0_Config2_TU = Param.Unsigned(0,"No Description")
-        CP0_Config2_TS = Param.Unsigned(0,"No Description")
-        CP0_Config2_TL = Param.Unsigned(0,"No Description")
-        CP0_Config2_TA = Param.Unsigned(0,"No Description")
-        CP0_Config2_SU = Param.Unsigned(0,"No Description")
-        CP0_Config2_SS = Param.Unsigned(0,"No Description")
-        CP0_Config2_SL = Param.Unsigned(0,"No Description")
-        CP0_Config2_SA = Param.Unsigned(0,"No Description")
-        CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
-        CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
-        CP0_Config3_LPA = Param.Bool(False,"No Description")
-        CP0_Config3_VEIC = Param.Bool(False,"No Description")
-        CP0_Config3_VInt = Param.Bool(False,"No Description")
-        CP0_Config3_SP = Param.Bool(False,"No Description")
-        CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
-        CP0_Config3_SM = Param.Bool(False,"No Description")
-        CP0_Config3_TL = Param.Bool(False,"No Description")
-        CP0_WatchHi_M = Param.Bool(False,"No Description")
-        CP0_PerfCtr_M = Param.Bool(False,"No Description")
-        CP0_PerfCtr_W = Param.Bool(False,"No Description")
-        CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
-        CP0_Config = Param.Unsigned(0,"CP0 Config Register")
-        CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
-        CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
-        CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index a56f3db24..8557b5bd5 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -239,8 +239,6 @@ class BaseCPU : public MemObject
      */
     ThreadID numThreads;
 
-    TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
-
     /**
      * Vector of per-thread instruction-based event queues.  Used for
      * scheduling events based on number of instructions committed by
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 0ec4c9861..1c2fc6333 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -315,8 +315,6 @@ InOrderCPU::InOrderCPU(Params *params)
         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
         isa[tid].clear();
 
-        isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
-
         // Define dummy instructions and resource requests to be used.
         dummyInst[tid] = new InOrderDynInst(this, 
                                             thread[tid], 
@@ -344,8 +342,6 @@ InOrderCPU::InOrderCPU(Params *params)
 #if FULL_SYSTEM
     Fault resetFault = new ResetFault();
     resetFault->invoke(tcBase());
-#else
-    reset();
 #endif
 
     
@@ -696,15 +692,6 @@ InOrderCPU::init()
     resPool->init();
 }
 
-void
-InOrderCPU::reset()
-{
-    for (int i = 0; i < numThreads; i++) {
-        isa[i].reset(coreType, numThreads,
-                     1/*numVirtProcs*/, dynamic_cast<BaseCPU*>(this));
-    }
-}
-
 Port*
 InOrderCPU::getPort(const std::string &if_name, int idx)
 {
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 2fa6bdc59..403c931b2 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -395,9 +395,6 @@ class InOrderCPU : public BaseCPU
     /** Initialize the CPU */
     void init();
 
-    /** Reset State in the CPU */
-    void reset();
-
     /** Get a Memory Port */
     Port* getPort(const std::string &if_name, int idx = 0);