Merge vm1.(none):/home/stever/bk/newmem-head

into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920

9 files changed, 31 insertions, 34 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 078ae1283..f86313da0 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -269,12 +269,10 @@ Tick
 BaseCPU::nextCycle(Tick begin_tick)
 {
     Tick next_tick = begin_tick;
-    next_tick -= (next_tick % clock);
+    if (next_tick % clock != 0)
+        next_tick = next_tick - (next_tick % clock) + clock;
     next_tick += phase;
 
-    while (next_tick < curTick)
-        next_tick += clock;
-
     assert(next_tick >= curTick);
     return next_tick;
 }
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 9b87f2e8a..85df19348 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -650,7 +650,7 @@ Trace::InstRecord::dump()
                              << endl;
 
                         predecoder.setTC(thread);
-                        predecoder.moreBytes(m5Pc, m5Pc, 0,
+                        predecoder.moreBytes(m5Pc, m5Pc,
                                 shared_data->instruction);
 
                         assert(predecoder.extMachInstReady());
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index e031faefa..e691cfe5d 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -55,7 +55,7 @@ class DerivO3CPU(BaseCPU):
             checker.itb = Parent.itb
             checker.dtb = Parent.dtb
 
-    cachePorts = Param.Unsigned("Cache Ports")
+    cachePorts = Param.Unsigned(200, "Cache Ports")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     _mem_ports = ['icache_port', 'dcache_port']
@@ -137,15 +137,15 @@ class DerivO3CPU(BaseCPU):
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
 
-    smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads")
-    smtFetchPolicy = Param.String("SMT Fetch policy")
-    smtLSQPolicy    = Param.String("SMT LSQ Sharing Policy")
-    smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter")
-    smtIQPolicy    = Param.String("SMT IQ Sharing Policy")
-    smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter")
-    smtROBPolicy   = Param.String("SMT ROB Sharing Policy")
-    smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter")
-    smtCommitPolicy = Param.String("SMT Commit Policy")
+    smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
+    smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
+    smtLSQPolicy    = Param.String('Partitioned', "SMT LSQ Sharing Policy")
+    smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
+    smtIQPolicy    = Param.String('Partitioned', "SMT IQ Sharing Policy")
+    smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
+    smtROBPolicy   = Param.String('Partitioned', "SMT ROB Sharing Policy")
+    smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
+    smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
 
     def addPrivateSplitL1Caches(self, ic, dc):
         BaseCPU.addPrivateSplitL1Caches(self, ic, dc)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index a775b66d5..9e1b5d132 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -204,19 +204,17 @@ FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
         _status = Idle;
     }
 
-    checker = NULL;
-
-    if (params->checker) {
 #if USE_CHECKER
+    if (params->checker) {
         BaseCPU *temp_checker = params->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
 #if FULL_SYSTEM
         checker->setSystem(params->system);
 #endif
-#else
-        panic("Checker enabled but not compiled in!");
-#endif // USE_CHECKER
+    } else {
+        checker = NULL;
     }
+#endif // USE_CHECKER
 
 #if !FULL_SYSTEM
     thread.resize(number_of_threads);
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index e71d05c8e..b7533e311 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -42,6 +42,7 @@
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "config/full_system.hh"
+#include "config/use_checker.hh"
 #include "cpu/activity.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
@@ -617,11 +618,13 @@ class FullO3CPU : public BaseO3CPU
     /** The global sequence number counter. */
     InstSeqNum globalSeqNum;//[Impl::MaxThreads];
 
+#if USE_CHECKER
     /** Pointer to the checker, which can dynamically verify
      * instruction results at run time.  This can be set to NULL if it
      * is not being used.
      */
     Checker<DynInstPtr> *checker;
+#endif
 
 #if FULL_SYSTEM
     /** Pointer to the system. */
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index ab55ec744..1ce5bd20f 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1128,7 +1128,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                         (&cacheData[tid][offset]));
 
             predecoder.setTC(cpu->thread[tid]->getTC());
-            predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
+            predecoder.moreBytes(fetch_PC, fetch_PC, inst);
 
             ext_inst = predecoder.getExtMachInst();
 
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ea1c7d87f..03ff1282b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -521,15 +521,15 @@ AtomicSimpleCPU::tick()
             dcache_access = false; // assume no dcache access
 
             //Fetch more instruction memory if necessary
-            if(predecoder.needMoreBytes())
-            {
+            //if(predecoder.needMoreBytes())
+            //{
                 icache_access = true;
                 ifetch_pkt->reinitFromRequest();
 
                 icache_latency = icachePort.sendAtomic(ifetch_pkt);
                 // ifetch_req is initialized to read the instruction directly
                 // into the CPU object's inst field.
-            }
+            //}
 
             preExecute();
 
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b7f60522f..9285aa7b5 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -379,11 +379,11 @@ BaseSimpleCPU::preExecute()
         //This should go away once the constructor can be set up properly
         predecoder.setTC(thread->getTC());
         //If more fetch data is needed, pass it in.
-        if(predecoder.needMoreBytes())
-            predecoder.moreBytes(thread->readPC(),
-                    (thread->readPC() & PCMask) + fetchOffset, 0, inst);
-        else
-            predecoder.process();
+        Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
+        //if(predecoder.needMoreBytes())
+            predecoder.moreBytes(thread->readPC(), fetchPC, inst);
+        //else
+        //    predecoder.process();
 
         //If an instruction is ready, decode it. Otherwise, we'll have to
         //fetch beyond the MachInst at the current pc.
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 1c79fcf6b..7698a588d 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -560,8 +560,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick mem_time = pkt->req->getTime();
-        Tick next_tick = cpu->nextCycle(mem_time);
+        Tick next_tick = cpu->nextCycle(curTick);
 
         if (next_tick == curTick)
             cpu->completeIfetch(pkt);
@@ -655,8 +654,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick mem_time = pkt->req->getTime();
-        Tick next_tick = cpu->nextCycle(mem_time);
+        Tick next_tick = cpu->nextCycle(curTick);
 
         if (next_tick == curTick)
             cpu->completeDataAccess(pkt);