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authorNilay Vaish <nilay@cs.wisc.edu>2014-10-20 16:47:55 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2014-10-20 16:47:55 -0500
commit922a9d8ed2488a3483dbbfff47a4f341fb707b7b (patch)
tree3755a7e9d522ee5937e75a9c40d6eb36a6967b1d /src/cpu
parentc6731e331a63db58f3745187c95342549232c752 (diff)
downloadgem5-922a9d8ed2488a3483dbbfff47a4f341fb707b7b.tar.xz
cpu: o3: corrects base FP and CC register index in removeThread()
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/cpu.cc12
1 files changed, 4 insertions, 8 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 6895355f0..fd51cd123 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -835,26 +835,22 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
// Unbind Int Regs from Rename Map
for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
-
scoreboard.unsetReg(phys_reg);
freeList.addReg(phys_reg);
}
// Unbind Float Regs from Rename Map
- int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
- for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
+ int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
+ for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
-
scoreboard.unsetReg(phys_reg);
freeList.addReg(phys_reg);
}
// Unbind condition-code Regs from Rename Map
- max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
- for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
- creg < max_reg; creg++) {
+ max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
+ for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
-
scoreboard.unsetReg(phys_reg);
freeList.addReg(phys_reg);
}