Use PacketPtr everywhere

--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711

21 files changed, 63 insertions, 63 deletions

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index c2c81bf9b..9cb6b032e 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -169,7 +169,7 @@ CheckerCPU::read(Addr addr, T &data, unsigned flags)
     // translate to physical address
     translateDataReadReq(memReq);
 
-    Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
+    PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
 
     pkt->dataStatic(&data);
 
@@ -256,7 +256,7 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         T inst_data;
 /*
         // This code would work if the LSQ allowed for snooping.
-        Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
+        PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
         pkt.dataStatic(&inst_data);
 
         dcachePort->sendFunctional(pkt);
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 7f1efc036..ba34c5cfc 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -181,7 +181,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
         }
 
         if (fault == NoFault) {
-            Packet *pkt = new Packet(memReq, Packet::ReadReq,
+            PacketPtr pkt = new Packet(memReq, Packet::ReadReq,
                                      Packet::Broadcast);
 
             pkt->dataStatic(&machInst);
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 23f2eacbc..1e0d07f9a 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -55,21 +55,21 @@ using namespace std;
 int TESTER_ALLOCATOR=0;
 
 bool
-MemTest::CpuPort::recvTiming(Packet *pkt)
+MemTest::CpuPort::recvTiming(PacketPtr pkt)
 {
     memtest->completeRequest(pkt);
     return true;
 }
 
 Tick
-MemTest::CpuPort::recvAtomic(Packet *pkt)
+MemTest::CpuPort::recvAtomic(PacketPtr pkt)
 {
     panic("MemTest doesn't expect recvAtomic callback!");
     return curTick;
 }
 
 void
-MemTest::CpuPort::recvFunctional(Packet *pkt)
+MemTest::CpuPort::recvFunctional(PacketPtr pkt)
 {
     //Do nothing if we see one come through
 //    if (curTick != 0)//Supress warning durring initialization
@@ -94,7 +94,7 @@ MemTest::CpuPort::recvRetry()
 }
 
 void
-MemTest::sendPkt(Packet *pkt) {
+MemTest::sendPkt(PacketPtr pkt) {
     if (atomic) {
         cachePort.sendAtomic(pkt);
         pkt->makeAtomicResponse();
@@ -204,7 +204,7 @@ printData(ostream &os, uint8_t *data, int nbytes)
 }
 
 void
-MemTest::completeRequest(Packet *pkt)
+MemTest::completeRequest(PacketPtr pkt)
 {
     MemTestSenderState *state =
         dynamic_cast<MemTestSenderState *>(pkt->senderState);
@@ -381,7 +381,7 @@ MemTest::tick()
                  << dec << curTick << endl;
         }
 
-        Packet *pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+        PacketPtr pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
         pkt->dataDynamicArray(new uint8_t[req->getSize()]);
         MemTestSenderState *state = new MemTestSenderState(result);
         pkt->senderState = state;
@@ -421,7 +421,7 @@ MemTest::tick()
                  << dec << curTick << endl;
         }
 */
-        Packet *pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+        PacketPtr pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
         uint8_t *pkt_data = new uint8_t[req->getSize()];
         pkt->dataDynamicArray(pkt_data);
         memcpy(pkt_data, &data, req->getSize());
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 5de41f0d8..4e88ecffd 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -102,11 +102,11 @@ class MemTest : public MemObject
 
       protected:
 
-        virtual bool recvTiming(Packet *pkt);
+        virtual bool recvTiming(PacketPtr pkt);
 
-        virtual Tick recvAtomic(Packet *pkt);
+        virtual Tick recvAtomic(PacketPtr pkt);
 
-        virtual void recvFunctional(Packet *pkt);
+        virtual void recvFunctional(PacketPtr pkt);
 
         virtual void recvStatusChange(Status status);
 
@@ -133,7 +133,7 @@ class MemTest : public MemObject
     };
 
 //    Request *dataReq;
-    Packet  *retryPkt;
+    PacketPtr retryPkt;
 //    MemInterface *cacheInterface;
 //    PhysicalMemory *mainMem;
 //    PhysicalMemory *checkMem;
@@ -184,9 +184,9 @@ class MemTest : public MemObject
     Stats::Scalar<> numCopiesStat;
 
     // called by MemCompleteEvent::process()
-    void completeRequest(Packet *pkt);
+    void completeRequest(PacketPtr pkt);
 
-    void sendPkt(Packet *pkt);
+    void sendPkt(PacketPtr pkt);
 
     void doRetry();
 
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 9dee610b6..294aadde8 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -86,7 +86,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     Fault initiateAcc();
 
     /** Completes the access.  Only valid for memory operations. */
-    Fault completeAcc(Packet *pkt);
+    Fault completeAcc(PacketPtr pkt);
 
   private:
     /** Initializes variables. */
diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh
index 2d1b4b309..b273a7b9b 100644
--- a/src/cpu/o3/alpha/dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha/dyn_inst_impl.hh
@@ -100,7 +100,7 @@ AlphaDynInst<Impl>::initiateAcc()
 
 template <class Impl>
 Fault
-AlphaDynInst<Impl>::completeAcc(Packet *pkt)
+AlphaDynInst<Impl>::completeAcc(PacketPtr pkt)
 {
     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 54b652813..da75bfecf 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -78,7 +78,7 @@ DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
 
 template<class Impl>
 bool
-DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
+DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         fetch->processCacheCompletion(pkt);
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 0aac466b5..1b207fdbc 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -219,7 +219,7 @@ class LSQUnit {
     void writeback(DynInstPtr &inst, PacketPtr pkt);
 
     /** Handles completing the send of a store to memory. */
-    void storePostSend(Packet *pkt);
+    void storePostSend(PacketPtr pkt);
 
     /** Completes the store at the specified index. */
     void completeStore(int store_idx);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 3f9db912f..d940d7cb3 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -763,7 +763,7 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
 
 template <class Impl>
 void
-LSQUnit<Impl>::storePostSend(Packet *pkt)
+LSQUnit<Impl>::storePostSend(PacketPtr pkt)
 {
     if (isStalled() &&
         storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index 06bdfcec4..aa30bfa1e 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -87,7 +87,7 @@ class MipsDynInst : public BaseDynInst<Impl>
     Fault initiateAcc();
 
     /** Completes the access.  Only valid for memory operations. */
-    Fault completeAcc(Packet *pkt);
+    Fault completeAcc(PacketPtr pkt);
 
   private:
     /** Initializes variables. */
diff --git a/src/cpu/o3/mips/dyn_inst_impl.hh b/src/cpu/o3/mips/dyn_inst_impl.hh
index 57dec1ccf..5bc01b9b3 100755
--- a/src/cpu/o3/mips/dyn_inst_impl.hh
+++ b/src/cpu/o3/mips/dyn_inst_impl.hh
@@ -100,7 +100,7 @@ MipsDynInst<Impl>::initiateAcc()
 
 template <class Impl>
 Fault
-MipsDynInst<Impl>::completeAcc(Packet *pkt)
+MipsDynInst<Impl>::completeAcc(PacketPtr pkt)
 {
     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index 75ac464ec..e7390626e 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -133,7 +133,7 @@ class OzoneDynInst : public BaseDynInst<Impl>
 
     Fault initiateAcc();
 
-    Fault completeAcc(Packet *pkt);
+    Fault completeAcc(PacketPtr pkt);
 
     // The register accessor methods provide the index of the
     // instruction's operand (e.g., 0 or 1), not the architectural
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index db1460eba..0a1e1c139 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -108,7 +108,7 @@ OzoneDynInst<Impl>::initiateAcc()
 
 template <class Impl>
 Fault
-OzoneDynInst<Impl>::completeAcc(Packet *pkt)
+OzoneDynInst<Impl>::completeAcc(PacketPtr pkt)
 {
     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index 59cf9785c..2bdca35b9 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -129,7 +129,7 @@ class FrontEnd
                 const bool is_branch = false, const bool branch_taken = false);
     DynInstPtr getInst();
 
-    void processCacheCompletion(Packet *pkt);
+    void processCacheCompletion(PacketPtr pkt);
 
     void addFreeRegs(int num_freed);
 
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index c814ff9c7..eed6de6dd 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -74,7 +74,7 @@ FrontEnd<Impl>::IcachePort::recvStatusChange(Status status)
 
 template<class Impl>
 bool
-FrontEnd<Impl>::IcachePort::recvTiming(Packet *pkt)
+FrontEnd<Impl>::IcachePort::recvTiming(PacketPtr pkt)
 {
     fe->processCacheCompletion(pkt);
     return true;
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 9b93ce74f..8307da521 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -222,7 +222,7 @@ class OzoneLWLSQ {
     void writeback(DynInstPtr &inst, PacketPtr pkt);
 
     /** Handles completing the send of a store to memory. */
-    void storePostSend(Packet *pkt, DynInstPtr &inst);
+    void storePostSend(PacketPtr pkt, DynInstPtr &inst);
 
     /** Completes the store at the specified index. */
     void completeStore(DynInstPtr &inst);
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index e523712da..1f3f18502 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -832,7 +832,7 @@ OzoneLWLSQ<Impl>::dumpInsts()
 
 template <class Impl>
 void
-OzoneLWLSQ<Impl>::storePostSend(Packet *pkt, DynInstPtr &inst)
+OzoneLWLSQ<Impl>::storePostSend(PacketPtr pkt, DynInstPtr &inst)
 {
     if (isStalled() &&
         inst->seqNum == stallingStoreIsn) {
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index fcda974e3..38a8ba097 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -93,21 +93,21 @@ AtomicSimpleCPU::init()
 }
 
 bool
-AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
+AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
 {
     panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
     return true;
 }
 
 Tick
-AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
+AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
 {
     //Snooping a coherence request, just return
     return curTick;
 }
 
 void
-AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
+AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
 {
     //No internal storage to update, just return
     return;
@@ -260,7 +260,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
     // use the CPU's statically allocated read request and packet objects
     Request *req = data_read_req;
-    Packet  *pkt = data_read_pkt;
+    PacketPtr pkt = data_read_pkt;
 
     req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 
@@ -342,7 +342,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     // use the CPU's statically allocated write request and packet objects
     Request *req = data_write_req;
-    Packet  *pkt = data_write_pkt;
+    PacketPtr pkt = data_write_pkt;
 
     req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 52afd76ef..0edca9369 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -92,11 +92,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
       protected:
 
-        virtual bool recvTiming(Packet *pkt);
+        virtual bool recvTiming(PacketPtr pkt);
 
-        virtual Tick recvAtomic(Packet *pkt);
+        virtual Tick recvAtomic(PacketPtr pkt);
 
-        virtual void recvFunctional(Packet *pkt);
+        virtual void recvFunctional(PacketPtr pkt);
 
         virtual void recvStatusChange(Status status);
 
@@ -110,12 +110,12 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     CpuPort icachePort;
     CpuPort dcachePort;
 
-    Request *ifetch_req;
-    Packet  *ifetch_pkt;
-    Request *data_read_req;
-    Packet  *data_read_pkt;
-    Request *data_write_req;
-    Packet  *data_write_pkt;
+    Request  *ifetch_req;
+    PacketPtr ifetch_pkt;
+    Request  *data_read_req;
+    PacketPtr data_read_pkt;
+    Request  *data_write_req;
+    PacketPtr data_write_pkt;
 
     bool dcache_access;
     Tick dcache_latency;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 3ddc938c3..97df0e5d5 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -66,14 +66,14 @@ TimingSimpleCPU::init()
 }
 
 Tick
-TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
+TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
 {
     panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
     return curTick;
 }
 
 void
-TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
+TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
 {
     //No internal storage to update, jusst return
     return;
@@ -90,7 +90,7 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
 
 
 void
-TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
+TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
 {
     pkt = _pkt;
     Event::schedule(t);
@@ -269,7 +269,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
     // Now do the access.
     if (fault == NoFault) {
-        Packet *pkt =
+        PacketPtr pkt =
             new Packet(req, Packet::ReadReq, Packet::Broadcast);
         pkt->dataDynamic<T>(new T);
 
@@ -471,7 +471,7 @@ TimingSimpleCPU::advanceInst(Fault fault)
 
 
 void
-TimingSimpleCPU::completeIfetch(Packet *pkt)
+TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 {
     // received a response from the icache: execute the received
     // instruction
@@ -527,7 +527,7 @@ TimingSimpleCPU::IcachePort::ITickEvent::process()
 }
 
 bool
-TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
+TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
@@ -555,7 +555,7 @@ TimingSimpleCPU::IcachePort::recvRetry()
     // waiting to transmit
     assert(cpu->ifetch_pkt != NULL);
     assert(cpu->_status == IcacheRetry);
-    Packet *tmp = cpu->ifetch_pkt;
+    PacketPtr tmp = cpu->ifetch_pkt;
     if (sendTiming(tmp)) {
         cpu->_status = IcacheWaitResponse;
         cpu->ifetch_pkt = NULL;
@@ -563,7 +563,7 @@ TimingSimpleCPU::IcachePort::recvRetry()
 }
 
 void
-TimingSimpleCPU::completeDataAccess(Packet *pkt)
+TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
 {
     // received a response from the dcache: complete the load or store
     // instruction
@@ -605,7 +605,7 @@ TimingSimpleCPU::completeDrain()
 }
 
 bool
-TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
+TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
@@ -639,7 +639,7 @@ TimingSimpleCPU::DcachePort::recvRetry()
     // waiting to transmit
     assert(cpu->dcache_pkt != NULL);
     assert(cpu->_status == DcacheRetry);
-    Packet *tmp = cpu->dcache_pkt;
+    PacketPtr tmp = cpu->dcache_pkt;
     if (sendTiming(tmp)) {
         cpu->_status = DcacheWaitResponse;
         // memory system takes ownership of packet
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 988ddeded..577e13e40 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -84,9 +84,9 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
       protected:
 
-        virtual Tick recvAtomic(Packet *pkt);
+        virtual Tick recvAtomic(PacketPtr pkt);
 
-        virtual void recvFunctional(Packet *pkt);
+        virtual void recvFunctional(PacketPtr pkt);
 
         virtual void recvStatusChange(Status status);
 
@@ -96,13 +96,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
         struct TickEvent : public Event
         {
-            Packet *pkt;
+            PacketPtr pkt;
             TimingSimpleCPU *cpu;
 
             TickEvent(TimingSimpleCPU *_cpu)
                 :Event(&mainEventQueue), cpu(_cpu) {}
             const char *description() { return "Timing CPU clock event"; }
-            void schedule(Packet *_pkt, Tick t);
+            void schedule(PacketPtr _pkt, Tick t);
         };
 
     };
@@ -117,7 +117,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
       protected:
 
-        virtual bool recvTiming(Packet *pkt);
+        virtual bool recvTiming(PacketPtr pkt);
 
         virtual void recvRetry();
 
@@ -144,7 +144,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
       protected:
 
-        virtual bool recvTiming(Packet *pkt);
+        virtual bool recvTiming(PacketPtr pkt);
 
         virtual void recvRetry();
 
@@ -163,8 +163,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
     IcachePort icachePort;
     DcachePort dcachePort;
 
-    Packet *ifetch_pkt;
-    Packet *dcache_pkt;
+    PacketPtr ifetch_pkt;
+    PacketPtr dcache_pkt;
 
     int cpu_id;
     Tick previousTick;
@@ -192,8 +192,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 
     void fetch();
-    void completeIfetch(Packet *);
-    void completeDataAccess(Packet *);
+    void completeIfetch(PacketPtr );
+    void completeDataAccess(PacketPtr );
     void advanceInst(Fault fault);
   private:
     void completeDrain();