Merge with head.

--HG--
extra : convert_revision : 1aa0e4569a7c10e6a395c2c951ac29275b5bcf59

23 files changed, 103 insertions, 59 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 7b31eb766..25bd3f893 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -74,7 +74,7 @@ CPUProgressEvent::process()
 {
     Counter temp = cpu->totalInstructions();
 #ifndef NDEBUG
-    double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1));
+    double ipc = double(temp - lastNumInst) / (interval / cpu->ticks(1));
 
     DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n",
              cpu->name(), temp - lastNumInst, ipc);
@@ -223,7 +223,7 @@ BaseCPU::startup()
 
     if (params->progress_interval) {
         new CPUProgressEvent(&mainEventQueue,
-                             cycles(params->progress_interval),
+                             ticks(params->progress_interval),
                              this);
     }
 }
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 76f6e4684..3c3e91523 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -82,8 +82,9 @@ class BaseCPU : public MemObject
   public:
 //    Tick currentTick;
     inline Tick frequency() const { return Clock::Frequency / clock; }
-    inline Tick cycles(int numCycles) const { return clock * numCycles; }
+    inline Tick ticks(int numCycles) const { return clock * numCycles; }
     inline Tick curCycle() const { return curTick / clock; }
+    inline Tick tickToCycles(Tick val) const { return val / clock; }
     // @todo remove me after debugging with legion done
     Tick instCount() { return instCnt; }
 
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 583fd5f8d..f8c8a0547 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -270,7 +270,7 @@ void
 MemTest::tick()
 {
     if (!tickEvent.scheduled())
-        tickEvent.schedule(curTick + cycles(1));
+        tickEvent.schedule(curTick + ticks(1));
 
     if (++noResponseCycles >= 500000) {
         cerr << name() << ": deadlocked at cycle " << curTick << endl;
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index fa168c70b..1c918df33 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -55,7 +55,7 @@ class MemTest : public MemObject
     // register statistics
     virtual void regStats();
 
-    inline Tick cycles(int numCycles) const { return numCycles; }
+    inline Tick ticks(int numCycles) const { return numCycles; }
 
     // main simulation loop (one cycle)
     void tick();
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index 1aa3d1618..f569c048b 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -80,8 +80,8 @@ DerivO3CPUParams::create()
     params->itb = itb;
     params->dtb = dtb;
 
-#if FULL_SYSTEM
     params->system = system;
+#if FULL_SYSTEM
     params->profile = profile;
 
     params->do_quiesce = do_quiesce;
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index 0799b9cb5..b9afb3f9f 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -88,9 +88,9 @@ O3CheckerParams::create()
 
     params->itb = itb;
     params->dtb = dtb;
-#if FULL_SYSTEM
     params->system = system;
     params->cpu_id = cpu_id;
+#if FULL_SYSTEM
     params->profile = profile;
 #else
     params->process = workload;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index f263383ae..89df257e9 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -325,7 +325,7 @@ DefaultCommit<Impl>::initStage()
     cpu->activateStage(O3CPU::CommitIdx);
 
     cpu->activityThisCycle();
-    trapLatency = cpu->cycles(trapLatency);
+    trapLatency = cpu->ticks(trapLatency);
 }
 
 template <class Impl>
@@ -910,25 +910,21 @@ DefaultCommit<Impl>::commitInsts()
                 microPC[tid] = nextMicroPC[tid];
                 nextMicroPC[tid] = microPC[tid] + 1;
 
-#if FULL_SYSTEM
                 int count = 0;
                 Addr oldpc;
+                // Debug statement.  Checks to make sure we're not
+                // currently updating state while handling PC events.
+                assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
                 do {
-                    // Debug statement.  Checks to make sure we're not
-                    // currently updating state while handling PC events.
-                    if (count == 0)
-                        assert(!thread[tid]->inSyscall &&
-                               !thread[tid]->trapPending);
                     oldpc = PC[tid];
-                    cpu->system->pcEventQueue.service(
-                        thread[tid]->getTC());
+                    cpu->system->pcEventQueue.service(thread[tid]->getTC());
                     count++;
                 } while (oldpc != PC[tid]);
                 if (count > 1) {
-                    DPRINTF(Commit, "PC skip function event, stopping commit\n");
+                    DPRINTF(Commit,
+                            "PC skip function event, stopping commit\n");
                     break;
                 }
-#endif
             } else {
                 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
                         "[tid:%i] [sn:%i].\n",
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 98e200944..3842d27bd 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -464,7 +464,7 @@ FullO3CPU<Impl>::tick()
             lastRunningCycle = curTick;
             timesIdled++;
         } else {
-            tickEvent.schedule(nextCycle(curTick + cycles(1)));
+            tickEvent.schedule(nextCycle(curTick + ticks(1)));
             DPRINTF(O3CPU, "Scheduling next tick!\n");
         }
     }
@@ -558,7 +558,7 @@ FullO3CPU<Impl>::activateContext(int tid, int delay)
     // Needs to set each stage to running as well.
     if (delay){
         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
-                "on cycle %d\n", tid, curTick + cycles(delay));
+                "on cycle %d\n", tid, curTick + ticks(delay));
         scheduleActivateThreadEvent(tid, delay);
     } else {
         activateThread(tid);
@@ -585,7 +585,7 @@ FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
     // Schedule removal of thread data from CPU
     if (delay){
         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
-                "on cycle %d\n", tid, curTick + cycles(delay));
+                "on cycle %d\n", tid, curTick + ticks(delay));
         scheduleDeallocateContextEvent(tid, remove, delay);
         return false;
     } else {
@@ -1409,7 +1409,8 @@ FullO3CPU<Impl>::wakeCPU()
 
     DPRINTF(Activity, "Waking up CPU\n");
 
-    idleCycles += (curTick - 1) - lastRunningCycle;
+    idleCycles += tickToCycles((curTick - 1) - lastRunningCycle);
+    numCycles += tickToCycles((curTick - 1) - lastRunningCycle);
 
     tickEvent.schedule(nextCycle());
 }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index d97a2080d..162e377e1 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -146,9 +146,9 @@ class FullO3CPU : public BaseO3CPU
     void scheduleTickEvent(int delay)
     {
         if (tickEvent.squashed())
-            tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
+            tickEvent.reschedule(nextCycle(curTick + ticks(delay)));
         else if (!tickEvent.scheduled())
-            tickEvent.schedule(nextCycle(curTick + cycles(delay)));
+            tickEvent.schedule(nextCycle(curTick + ticks(delay)));
     }
 
     /** Unschedule tick event, regardless of its current state. */
@@ -187,10 +187,10 @@ class FullO3CPU : public BaseO3CPU
         // Schedule thread to activate, regardless of its current state.
         if (activateThreadEvent[tid].squashed())
             activateThreadEvent[tid].
-                reschedule(nextCycle(curTick + cycles(delay)));
+                reschedule(nextCycle(curTick + ticks(delay)));
         else if (!activateThreadEvent[tid].scheduled())
             activateThreadEvent[tid].
-                schedule(nextCycle(curTick + cycles(delay)));
+                schedule(nextCycle(curTick + ticks(delay)));
     }
 
     /** Unschedule actiavte thread event, regardless of its current state. */
@@ -238,10 +238,10 @@ class FullO3CPU : public BaseO3CPU
         // Schedule thread to activate, regardless of its current state.
         if (deallocateContextEvent[tid].squashed())
             deallocateContextEvent[tid].
-                reschedule(nextCycle(curTick + cycles(delay)));
+                reschedule(nextCycle(curTick + ticks(delay)));
         else if (!deallocateContextEvent[tid].scheduled())
             deallocateContextEvent[tid].
-                schedule(nextCycle(curTick + cycles(delay)));
+                schedule(nextCycle(curTick + ticks(delay)));
     }
 
     /** Unschedule thread deallocation in CPU */
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 47f019ebe..aea62f12d 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -752,7 +752,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
                 FUCompletion *execution = new FUCompletion(issuing_inst,
                                                            idx, this);
 
-                execution->schedule(curTick + cpu->cycles(issue_latency - 1));
+                execution->schedule(curTick + cpu->ticks(issue_latency - 1));
 
                 // @todo: Enforce that issue_latency == 1 or op_latency
                 if (issue_latency > 1) {
diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc
index b7c684431..b08845b4e 100644
--- a/src/cpu/o3/sparc/cpu_builder.cc
+++ b/src/cpu/o3/sparc/cpu_builder.cc
@@ -81,8 +81,8 @@ DerivO3CPUParams::create()
     params->itb = itb;
     params->dtb = dtb;
 
-#if FULL_SYSTEM
     params->system = system;
+#if FULL_SYSTEM
     params->profile = profile;
 
     params->do_quiesce = do_quiesce;
diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index 625b2a39a..37b9f951a 100644
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -89,9 +89,9 @@ OzoneCheckerParams::create()
 
     params->itb = itb;
     params->dtb = dtb;
-#if FULL_SYSTEM
     params->system = system;
     params->cpu_id = cpu_id;
+#if FULL_SYSTEM
     params->profile = profile;
 #else
     params->process = workload;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 78d0892c4..036db1351 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -315,9 +315,9 @@ class OzoneCPU : public BaseCPU
     void scheduleTickEvent(int delay)
     {
         if (tickEvent.squashed())
-            tickEvent.reschedule(curTick + cycles(delay));
+            tickEvent.reschedule(curTick + ticks(delay));
         else if (!tickEvent.scheduled())
-            tickEvent.schedule(curTick + cycles(delay));
+            tickEvent.schedule(curTick + ticks(delay));
     }
 
     /// Unschedule tick event, regardless of its current state.
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 7edbe41c9..beb179d41 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -82,9 +82,9 @@ DerivOzoneCPUParams::create()
     params->itb = itb;
     params->dtb = dtb;
 
-#if FULL_SYSTEM
     params->system = system;
     params->cpu_id = cpu_id;
+#if FULL_SYSTEM
     params->profile = profile;
     params->do_quiesce = do_quiesce;
     params->do_checkpoint_insts = do_checkpoint_insts;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 37a91c630..5080c54f6 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -613,7 +613,7 @@ OzoneCPU<Impl>::tick()
     comInstEventQueue[0]->serviceEvents(numInst);
 
     if (!tickEvent.scheduled() && _status == Running)
-        tickEvent.schedule(curTick + cycles(1));
+        tickEvent.schedule(curTick + ticks(1));
 }
 
 template <class Impl>
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index f84bda348..42788cee1 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -45,7 +45,7 @@ LWBackEnd<Impl>::generateTrapEvent(Tick latency)
 
     TrapEvent *trap = new TrapEvent(this);
 
-    trap->schedule(curTick + cpu->cycles(latency));
+    trap->schedule(curTick + cpu->ticks(latency));
 
     thread->trapPending = true;
 }
diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc
index ca55cdca4..9cd56fdb4 100644
--- a/src/cpu/ozone/simple_cpu_builder.cc
+++ b/src/cpu/ozone/simple_cpu_builder.cc
@@ -85,10 +85,9 @@ SimpleOzoneCPUParams::create()
     params->itb = itb;
     params->dtb = dtb;
 
-#if FULL_SYSTEM
     params->system = system;
     params->cpu_id = cpu_id;
-#else
+#if !FULL_SYSTEM
     params->workload = workload;
 //    params->pTable = page_table;
 #endif // FULL_SYSTEM
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 06f52e30e..525bcbd22 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -252,9 +252,10 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
     assert(!tickEvent.scheduled());
 
     notIdleFraction++;
+    numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
 
     //Make sure ticks are still on multiples of cycles
-    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
+    tickEvent.schedule(nextCycle(curTick + ticks(delay)));
     _status = Running;
 }
 
@@ -584,7 +585,7 @@ AtomicSimpleCPU::tick()
 {
     DPRINTF(SimpleCPU, "Tick\n");
 
-    Tick latency = cycles(1); // instruction takes one cycle by default
+    Tick latency = ticks(1); // instruction takes one cycle by default
 
     for (int i = 0; i < width; ++i) {
         numCycles++;
@@ -642,14 +643,14 @@ AtomicSimpleCPU::tick()
 
             if (simulate_stalls) {
                 Tick icache_stall =
-                    icache_access ? icache_latency - cycles(1) : 0;
+                    icache_access ? icache_latency - ticks(1) : 0;
                 Tick dcache_stall =
-                    dcache_access ? dcache_latency - cycles(1) : 0;
-                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
-                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
-                    latency += cycles(stall_cycles+1);
+                    dcache_access ? dcache_latency - ticks(1) : 0;
+                Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
+                if (ticks(stall_cycles) < (icache_stall + dcache_stall))
+                    latency += ticks(stall_cycles+1);
                 else
-                    latency += cycles(stall_cycles);
+                    latency += ticks(stall_cycles);
             }
 
         }
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index f3b34880e..68c6e12ea 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -494,12 +494,10 @@ BaseSimpleCPU::advancePC(Fault fault)
         }
     }
 
-#if FULL_SYSTEM
     Addr oldpc;
     do {
         oldpc = thread->readPC();
         system->pcEventQueue.service(tc);
     } while (oldpc != thread->readPC());
-#endif
 }
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 8d1cf9a17..30100e6c9 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -29,6 +29,7 @@
  */
 
 #include "arch/locked_mem.hh"
+#include "arch/mmaped_ipr.hh"
 #include "arch/utility.hh"
 #include "base/bigint.hh"
 #include "cpu/exetrace.hh"
@@ -172,7 +173,6 @@ TimingSimpleCPU::resume()
     }
 
     changeState(SimObject::Running);
-    previousTick = curTick;
 }
 
 void
@@ -180,7 +180,7 @@ TimingSimpleCPU::switchOut()
 {
     assert(status() == Running || status() == Idle);
     _status = SwitchedOut;
-    numCycles += curTick - previousTick;
+    numCycles += tickToCycles(curTick - previousTick);
 
     // If we've been scheduled to resume but are then told to switch out,
     // we'll need to cancel it.
@@ -207,6 +207,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
     if (_status != Running) {
         _status = Idle;
     }
+    previousTick = curTick;
 }
 
 
@@ -222,7 +223,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
     _status = Running;
 
     // kick things off by initiating the fetch of the next instruction
-    fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
+    fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay)));
 }
 
 
@@ -266,7 +267,13 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
                        Packet::Broadcast);
         pkt->dataDynamic<T>(new T);
 
-        if (!dcachePort.sendTiming(pkt)) {
+        if (req->isMmapedIpr()) {
+            Tick delay;
+            delay = TheISA::handleIprRead(thread->getTC(), pkt);
+            new IprEvent(pkt, this, nextCycle(curTick + delay));
+            _status = DcacheWaitResponse;
+            dcache_pkt = NULL;
+        } else if (!dcachePort.sendTiming(pkt)) {
             _status = DcacheRetry;
             dcache_pkt = pkt;
         } else {
@@ -375,7 +382,14 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         dcache_pkt->set(data);
 
         if (do_access) {
-            if (!dcachePort.sendTiming(dcache_pkt)) {
+            if (req->isMmapedIpr()) {
+                Tick delay;
+                dcache_pkt->set(htog(data));
+                delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
+                new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
+                _status = DcacheWaitResponse;
+                dcache_pkt = NULL;
+            } else if (!dcachePort.sendTiming(dcache_pkt)) {
                 _status = DcacheRetry;
             } else {
                 _status = DcacheWaitResponse;
@@ -483,7 +497,7 @@ TimingSimpleCPU::fetch()
         advanceInst(fault);
     }
 
-    numCycles += curTick - previousTick;
+    numCycles += tickToCycles(curTick - previousTick);
     previousTick = curTick;
 }
 
@@ -512,7 +526,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 
     _status = Running;
 
-    numCycles += curTick - previousTick;
+    numCycles += tickToCycles(curTick - previousTick);
     previousTick = curTick;
 
     if (getState() == SimObject::Draining) {
@@ -551,6 +565,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
             }
 
             postExecute();
+            // @todo remove me after debugging with legion done
+            if (curStaticInst && (!curStaticInst->isMicroop() ||
+                        curStaticInst->isFirstMicroop()))
+                instCnt++;
             advanceInst(fault);
         }
     } else {
@@ -567,6 +585,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
         }
 
         postExecute();
+        // @todo remove me after debugging with legion done
+        if (curStaticInst && (!curStaticInst->isMicroop() ||
+                    curStaticInst->isFirstMicroop()))
+            instCnt++;
         advanceInst(fault);
     }
 
@@ -629,7 +651,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
     assert(_status == DcacheWaitResponse);
     _status = Running;
 
-    numCycles += curTick - previousTick;
+    numCycles += tickToCycles(curTick - previousTick);
     previousTick = curTick;
 
     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
@@ -730,6 +752,24 @@ TimingSimpleCPU::DcachePort::recvRetry()
     }
 }
 
+TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
+    : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu)
+{
+    schedule(t);
+}
+
+void
+TimingSimpleCPU::IprEvent::process()
+{
+    cpu->completeDataAccess(pkt);
+}
+
+const char *
+TimingSimpleCPU::IprEvent::description()
+{
+    return "Timing Simple CPU Delay IPR event";
+}
+
 
 ////////////////////////////////////////////////////////////////////////
 //
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index ba194b3fa..4a4c276fd 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -203,6 +203,14 @@ class TimingSimpleCPU : public BaseSimpleCPU
     typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
     FetchEvent *fetchEvent;
 
+    struct IprEvent : Event {
+        Packet *pkt;
+        TimingSimpleCPU *cpu;
+        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
+        virtual void process();
+        virtual const char *description();
+    };
+
     void completeDrain();
 };
 
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index e5739b2ce..d3cf34e9d 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -110,10 +110,10 @@ TraceCPU::tick()
         if (mainEventQueue.empty()) {
             exitSimLoop("end of memory trace reached");
         } else {
-            tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
+            tickEvent.schedule(mainEventQueue.nextEventTime() + ticks(1));
         }
     } else {
-        tickEvent.schedule(max(curTick + cycles(1), nextCycle));
+        tickEvent.schedule(max(curTick + ticks(1), nextCycle));
     }
 }
 
diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index 9c96d71d5..b88c7072e 100644
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -107,7 +107,7 @@ class TraceCPU : public SimObject
              MemInterface *dcache_interface,
              MemTraceReader *data_trace);
 
-    inline Tick cycles(int numCycles) { return numCycles; }
+    inline Tick ticks(int numCycles) { return numCycles; }
 
     /**
      * Perform all the accesses for one cycle.