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authorNathan Binkert <nate@binkert.org>2010-06-14 23:24:46 -0700
committerNathan Binkert <nate@binkert.org>2010-06-14 23:24:46 -0700
commit54d813adcaf6d5eda4040c20bae1706b0a78324b (patch)
treef0a6062071673958771183320e5ddd7a8deca42d /src/cpu
parent420402c0a314f515ff1e84d6c6da4892e006c92e (diff)
downloadgem5-54d813adcaf6d5eda4040c20bae1706b0a78324b.tar.xz
stats: get rid of the never-really-used event stuff
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/ozone/back_end.hh8
-rw-r--r--src/cpu/ozone/inorder_back_end.hh16
-rw-r--r--src/cpu/simple/base.cc1
3 files changed, 0 insertions, 25 deletions
diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh
index ca858ce2e..d8afb1526 100644
--- a/src/cpu/ozone/back_end.hh
+++ b/src/cpu/ozone/back_end.hh
@@ -492,10 +492,6 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
}
}
*/
-/*
- if (!dcacheInterface && (memReq->isUncacheable()))
- recordEvent("Uncached Read");
-*/
return LSQ.read(req, data, load_idx);
}
@@ -533,10 +529,6 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
if (res && (fault == NoFault))
*res = memReq->result;
*/
-/*
- if (!dcacheInterface && (memReq->isUncacheable()))
- recordEvent("Uncached Write");
-*/
return LSQ.write(req, data, store_idx);
}
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index f242645a2..28e02bafb 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -229,10 +229,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
DPRINTF(IBE, "Dcache hit!\n");
}
}
-/*
- if (!dcacheInterface && (memReq->isUncacheable()))
- recordEvent("Uncached Read");
-*/
return fault;
}
@@ -269,10 +265,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
if (res && (fault == NoFault))
*res = memReq->result;
-/*
- if (!dcacheInterface && (memReq->isUncacheable()))
- recordEvent("Uncached Write");
-*/
return fault;
}
@@ -313,10 +305,6 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
}
}
-/*
- if (!dcacheInterface && (req->isUncacheable()))
- recordEvent("Uncached Read");
-*/
return NoFault;
}
@@ -390,10 +378,6 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
if (res && (fault == NoFault))
*res = req->result;
*/
-/*
- if (!dcacheInterface && (req->isUncacheable()))
- recordEvent("Uncached Write");
-*/
return NoFault;
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 7f40138d2..d7fc81de6 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -49,7 +49,6 @@
#include "base/misc.hh"
#include "base/pollevent.hh"
#include "base/range.hh"
-#include "base/stats/events.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "config/the_isa.hh"