summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorAkash Bagdia <akash.bagdia@arm.com>2013-06-27 05:49:49 -0400
committerAkash Bagdia <akash.bagdia@arm.com>2013-06-27 05:49:49 -0400
commit7eccb1b779cb6458ed78ba73f2fdabe94fa805b3 (patch)
treea47dc043defd5ff0afad3bdf103bc1a147dc0091 /src/cpu
parentf821c5472b5e524053846bd57b83c81238be159f (diff)
downloadgem5-7eccb1b779cb6458ed78ba73f2fdabe94fa805b3.tar.xz
config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for certain instances of CoherentBus, NonCoherentBus and IOCache where the specified clock is same as the default value of the system clock. As all the values used are the defaults, there are no performance changes. There are similar cases where the toL2Bus is set to use the parent CPU clock which is already the default behaviour. The main motivation for these simplifications is to ease the introduction of clock domains.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/BaseCPU.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index f52c6b11f..e7613c5bb 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -281,10 +281,10 @@ class BaseCPU(MemObject):
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
- # Override the default bus clock of 1 GHz and uses the CPU
- # clock for the L1-to-L2 bus, and also set a width of 32 bytes
- # (256-bits), which is four times that of the default bus.
- self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
+ # Set a width of 32 bytes (256-bits), which is four times that
+ # of the default bus. The clock of the CPU is inherited by
+ # default.
+ self.toL2Bus = CoherentBus(width = 32)
self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
self.toL2Bus.master = self.l2cache.cpu_side