summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2007-03-29 12:02:57 -0400
committerKevin Lim <ktlim@umich.edu>2007-03-29 12:02:57 -0400
commit80af6530f65551c7f47bf62f10093e6e420b47f2 (patch)
tree1c17a1d6f229a58a6bcd4d9517a7b0e4a1cfbffb /src/cpu
parent14a7cda195db9fcc6accca62bf2b8dfdb2218e0e (diff)
downloadgem5-80af6530f65551c7f47bf62f10093e6e420b47f2.tar.xz
Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. This fixes the segfault Ali recently found when using sampling.
src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. --HG-- extra : convert_revision : 04bcef44e754735d821509ebd69b0ef9c8ef8e2c
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/fetch.hh5
-rw-r--r--src/cpu/o3/fetch_impl.hh38
2 files changed, 32 insertions, 11 deletions
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index da7ce00f5..811f4d2bc 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -86,6 +86,8 @@ class DefaultFetch
bool snoopRangeSent;
+ virtual void setPeer(Port *port);
+
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);
@@ -184,6 +186,9 @@ class DefaultFetch
/** Initialize stage. */
void initStage();
+ /** Tells the fetch stage that the Icache is set. */
+ void setIcache();
+
/** Processes cache completion event. */
void processCacheCompletion(PacketPtr pkt);
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 663cd3142..34b06420d 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -51,6 +51,15 @@
#include <algorithm>
template<class Impl>
+void
+DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
+{
+ Port::setPeer(port);
+
+ fetch->setIcache();
+}
+
+template<class Impl>
Tick
DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
{
@@ -323,12 +332,6 @@ DefaultFetch<Impl>::initStage()
nextNPC[tid] = cpu->readNextNPC(tid);
}
- // Size of cache block.
- cacheBlkSize = icachePort->peerBlockSize();
-
- // Create mask to get rid of offset bits.
- cacheBlkMask = (cacheBlkSize - 1);
-
for (int tid=0; tid < numThreads; tid++) {
fetchStatus[tid] = Running;
@@ -337,11 +340,6 @@ DefaultFetch<Impl>::initStage()
memReq[tid] = NULL;
- // Create space to store a cache line.
- cacheData[tid] = new uint8_t[cacheBlkSize];
- cacheDataPC[tid] = 0;
- cacheDataValid[tid] = false;
-
stalls[tid].decode = false;
stalls[tid].rename = false;
stalls[tid].iew = false;
@@ -351,6 +349,24 @@ DefaultFetch<Impl>::initStage()
template<class Impl>
void
+DefaultFetch<Impl>::setIcache()
+{
+ // Size of cache block.
+ cacheBlkSize = icachePort->peerBlockSize();
+
+ // Create mask to get rid of offset bits.
+ cacheBlkMask = (cacheBlkSize - 1);
+
+ for (int tid=0; tid < numThreads; tid++) {
+ // Create space to store a cache line.
+ cacheData[tid] = new uint8_t[cacheBlkSize];
+ cacheDataPC[tid] = 0;
+ cacheDataValid[tid] = false;
+ }
+}
+
+template<class Impl>
+void
DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
{
unsigned tid = pkt->req->getThreadNum();