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authorRekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com>2017-07-18 16:31:38 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-07-19 10:01:15 +0000
commitc0875dfc398780a05dec68bbe36a17f73a98e030 (patch)
tree55af0f398cbd2dcd08d6cd3b5c3dd8ff65a85fb6 /src/cpu
parentdb522eb930020a7a9caf1ea6e289fc81a0bcc842 (diff)
downloadgem5-c0875dfc398780a05dec68bbe36a17f73a98e030.tar.xz
cpu: Add missing rename of vector registers in the O3 CPU
The introduction of a new vector register class broke rename in the O3 CPU due to an unhandled register class in DefaultRename<Impl>::renameSrcRegs(). This patch fixes adds the necessary handling to avoid a panic when the vector register file is used. Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4140 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/rename_impl.hh3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index b9adcdff7..bc024f603 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -1028,6 +1028,9 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
case FloatRegClass:
fpRenameLookups++;
break;
+ case VecRegClass:
+ vecRenameLookups++;
+ break;
case CCRegClass:
case MiscRegClass:
break;