Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 0756f7f1f63fae472e0ef1d20e9eb38e56de78c8

7 files changed, 17 insertions, 27 deletions

diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
index 55b975142..d7f3d5801 100644
--- a/src/cpu/o3/alpha_cpu.hh
+++ b/src/cpu/o3/alpha_cpu.hh
@@ -384,8 +384,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
     bool inPalMode(uint64_t PC)
     { return AlphaISA::PcPAL(PC); }
 
-    /** Traps to handle given fault. */
-    void trap(Fault fault, unsigned tid);
     bool simPalCheck(int palFunc, unsigned tid);
 
     /** Processes any interrupts. */
@@ -395,6 +393,8 @@ class AlphaO3CPU : public FullO3CPU<Impl>
     void halt() { panic("Halt not implemented!\n"); }
 #endif
 
+    /** Traps to handle given fault. */
+    void trap(Fault fault, unsigned tid);
 
 #if !FULL_SYSTEM
     /** Executes a syscall.
diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh
index 532611fb6..eca6fbbcb 100644
--- a/src/cpu/o3/alpha_cpu_impl.hh
+++ b/src/cpu/o3/alpha_cpu_impl.hh
@@ -755,14 +755,6 @@ AlphaO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
 
 template <class Impl>
 void
-AlphaO3CPU<Impl>::trap(Fault fault, unsigned tid)
-{
-    // Pass the thread's TC into the invoke method.
-    fault->invoke(this->threadContexts[tid]);
-}
-
-template <class Impl>
-void
 AlphaO3CPU<Impl>::processInterrupts()
 {
     // Check for interrupts here.  For now can copy the code that
@@ -823,6 +815,14 @@ AlphaO3CPU<Impl>::processInterrupts()
 
 #endif // FULL_SYSTEM
 
+template <class Impl>
+void
+AlphaO3CPU<Impl>::trap(Fault fault, unsigned tid)
+{
+    // Pass the thread's TC into the invoke method.
+    fault->invoke(this->threadContexts[tid]);
+}
+
 #if !FULL_SYSTEM
 
 template <class Impl>
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 176f83246..cd7dd47d4 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -991,7 +991,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
     if (inst_fault != NoFault) {
         head_inst->setCompleted();
-#if FULL_SYSTEM
         DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
                 head_inst->seqNum, head_inst->readPC());
 
@@ -1035,10 +1034,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
         generateTrapEvent(tid);
 
         return false;
-#else // !FULL_SYSTEM
-        panic("fault (%d) detected @ PC %08p", inst_fault,
-              head_inst->PC);
-#endif // FULL_SYSTEM
     }
 
     updateComInstStats(head_inst);
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 790c28f09..7fcd21b7d 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -36,7 +36,7 @@
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "cpu/pc_event.hh"
-#include "mem/packet.hh"
+#include "mem/packet_impl.hh"
 #include "mem/port.hh"
 #include "sim/eventq.hh"
 
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 9b67e61f2..74b8fe5bb 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -40,7 +40,7 @@
 #include "config/full_system.hh"
 #include "base/hashmap.hh"
 #include "cpu/inst_seq.hh"
-#include "mem/packet.hh"
+#include "mem/packet_impl.hh"
 #include "mem/port.hh"
 
 /**
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 7be74e97e..be6f421b3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -407,15 +407,14 @@ AtomicSimpleCPU::tick()
             postExecute();
 
             if (simulate_stalls) {
-                // This calculation assumes that the icache and dcache
-                // access latencies are always a multiple of the CPU's
-                // cycle time.  If not, the next tick event may get
-                // scheduled at a non-integer multiple of the CPU
-                // cycle time.
                 Tick icache_stall = icache_latency - cycles(1);
                 Tick dcache_stall =
                     dcache_access ? dcache_latency - cycles(1) : 0;
-                latency += icache_stall + dcache_stall;
+                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
+                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
+                    latency += cycles(stall_cycles+1);
+                else
+                    latency += cycles(stall_cycles);
             }
 
         }
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b4258fce6..db5dd2acf 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -446,11 +446,7 @@ void
 BaseSimpleCPU::advancePC(Fault fault)
 {
     if (fault != NoFault) {
-#if FULL_SYSTEM
         fault->invoke(tc);
-#else // !FULL_SYSTEM
-        fatal("fault (%s) detected @ PC %08p", fault->name(), thread->readPC());
-#endif // FULL_SYSTEM
     }
     else {
         // go to the next instruction