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authorNilay Vaish <nilay@cs.wisc.edu>2012-02-10 08:37:31 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-02-10 08:37:31 -0600
commit6a7a6263e16cd3a16b4d7738f7df06f6e7a97ed6 (patch)
treed47d2f929ab15a85192ca5a692b6d14fbd2a0da6 /src/cpu
parentcd765c23a2030d45223952315b4e862999714890 (diff)
downloadgem5-6a7a6263e16cd3a16b4d7738f7df06f6e7a97ed6.tar.xz
O3 CPU: Improve handling of delayed commit flag
The delayed commit flag is used in conjunction with interrupt pending flag to figure out whether or not fetch stage should get more instructions. This patch clears this flag when instructions are squashed. Also, in case an interrupt is pending, currently it is not possible to access the instruction cache. This patch allows accessing the cache in case this flag is set.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/fetch_impl.hh9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 72d9e960e..0b4067f7e 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -544,7 +544,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
tid);
return false;
- } else if (checkInterrupt(pc)) {
+ } else if (checkInterrupt(pc) && !delayedCommit[tid]) {
// Hold off fetch from getting new instructions when:
// Cache is blocked, or
// while an interrupt is pending and we're not in PAL mode, or
@@ -721,6 +721,13 @@ DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
fetchStatus[tid] = Squashing;
+ // microops are being squashed, it is not known wheather the
+ // youngest non-squashed microop was marked delayed commit
+ // or not. Setting the flag to true ensures that the
+ // interrupts are not handled when they cannot be, though
+ // some opportunities to handle interrupts may be missed.
+ delayedCommit[tid] = true;
+
++fetchSquashCycles;
}