Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its

python type of a latency.  In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.

8 files changed, 3 insertions, 15 deletions

diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py
index 06df9c1b1..bff9af62d 100644
--- a/src/cpu/CheckerCPU.py
+++ b/src/cpu/CheckerCPU.py
@@ -40,5 +40,3 @@ class CheckerCPU(BaseCPU):
         "If a load result is incorrect, only print a warning and do not exit")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index f79b79350..7b6404419 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -357,7 +357,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
 
 
 #if FULL_SYSTEM
-BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval)
+BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
     : Event(&mainEventQueue), cpu(_cpu), interval(_interval)
 { }
 
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 6e9e1dc39..251adc1b7 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -122,10 +122,10 @@ class BaseCPU : public MemObject
     {
       private:
         BaseCPU *cpu;
-        int interval;
+        Tick interval;
 
       public:
-        ProfileEvent(BaseCPU *cpu, int interval);
+        ProfileEvent(BaseCPU *cpu, Tick interval);
         void process();
     };
     ProfileEvent *profileEvent;
diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py
index 43a71d67b..edc6dc9b6 100644
--- a/src/cpu/o3/O3Checker.py
+++ b/src/cpu/o3/O3Checker.py
@@ -39,5 +39,3 @@ class O3Checker(BaseCPU):
         "If a load result is incorrect, only print a warning and do not exit")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
diff --git a/src/cpu/ozone/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py
index b9cfb448f..37386898d 100644
--- a/src/cpu/ozone/OzoneCPU.py
+++ b/src/cpu/ozone/OzoneCPU.py
@@ -40,8 +40,6 @@ class DerivOzoneCPU(BaseCPU):
 
     if build_env['USE_CHECKER']:
         checker = Param.BaseCPU("Checker CPU")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
 
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
diff --git a/src/cpu/ozone/OzoneChecker.py b/src/cpu/ozone/OzoneChecker.py
index f20b8770e..bfa39ead9 100644
--- a/src/cpu/ozone/OzoneChecker.py
+++ b/src/cpu/ozone/OzoneChecker.py
@@ -39,5 +39,3 @@ class OzoneChecker(BaseCPU):
         "If a load result is incorrect, only print a warning and do not exit")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index e1c1e4cd1..87e8b5509 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -37,8 +37,6 @@ class AtomicSimpleCPU(BaseSimpleCPU):
     simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     physmem_port = Port("Physical Memory Port")
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index f2b14a175..b7f044bfa 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -34,8 +34,6 @@ class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']