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authorKorey Sewell <ksewell@umich.edu>2010-03-27 01:40:05 -0400
committerKorey Sewell <ksewell@umich.edu>2010-03-27 01:40:05 -0400
commitac316d45e8818679efae8559eace010ae0487a99 (patch)
tree13287d3ad008ee079711d8f81d8f61629019a98f /src/cpu
parentd484e1b334c6fd3f2721a2a4628c2324ed14fd08 (diff)
downloadgem5-ac316d45e8818679efae8559eace010ae0487a99.tar.xz
inorder: write-hints bug fix
make sure to only read 1 src reg. for write-hint and any other similar 'store' instruction. Reading the source reg when its not necessary can cause the simulator to read from uninitialized values
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/inorder/pipeline_traits.cc4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/inorder/pipeline_traits.cc b/src/cpu/inorder/pipeline_traits.cc
index 8ff26dce2..397170163 100644
--- a/src/cpu/inorder/pipeline_traits.cc
+++ b/src/cpu/inorder/pipeline_traits.cc
@@ -116,7 +116,9 @@ bool createBackEndSchedule(DynInstPtr &inst)
if ( inst->isLoad() ) {
M->needs(DCache, CacheUnit::InitiateReadData);
} else if ( inst->isStore() ) {
- M->needs(RegManager, UseDefUnit::ReadSrcReg, 1);
+ if ( inst->numSrcRegs() >= 2 ) {
+ M->needs(RegManager, UseDefUnit::ReadSrcReg, 1);
+ }
M->needs(AGEN, AGENUnit::GenerateAddr);
M->needs(DCache, CacheUnit::InitiateWriteData);
}