arch: Make readMiscRegNoEffect const throughout

Finally took the plunge and made this apply to all ISAs, not just ARM.

9 files changed, 10 insertions, 10 deletions

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 49f44ff00..bed3b9e32 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -285,7 +285,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     MicroPC microPC() { return thread->microPC(); }
     //////////////////////////////////////////
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     {
         return thread->readMiscRegNoEffect(misc_reg);
     }
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index ccf0d3c1d..26d0dfa8b 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -275,7 +275,7 @@ class CheckerThreadContext : public ThreadContext
     MicroPC microPC()
     { return actualTC->microPC(); }
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     { return actualTC->readMiscRegNoEffect(misc_reg); }
 
     MiscReg readMiscReg(int misc_reg)
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 41345d3bd..80d5d9872 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -187,7 +187,7 @@ class ExecContext : public ::ExecContext
     }
 
     TheISA::MiscReg
-    readMiscRegNoEffect(int misc_reg)
+    readMiscRegNoEffect(int misc_reg) const
     {
         return thread.readMiscRegNoEffect(misc_reg);
     }
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b48c66c37..434bfd7da 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1205,7 +1205,7 @@ FullO3CPU<Impl>::verifyMemoryMode() const
 
 template <class Impl>
 TheISA::MiscReg
-FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
 {
     return this->isa[tid]->readMiscRegNoEffect(misc_reg);
 }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 09b7db867..5b33285c4 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -403,7 +403,7 @@ class FullO3CPU : public BaseO3CPU
     /** Register accessors.  Index refers to the physical register index. */
 
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 952d365bf..87d87900c 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -228,7 +228,7 @@ class O3ThreadContext : public ThreadContext
     { return cpu->microPC(thread->threadId()); }
 
     /** Reads a miscellaneous register. */
-    virtual MiscReg readMiscRegNoEffect(int misc_reg)
+    virtual MiscReg readMiscRegNoEffect(int misc_reg) const
     { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
 
     /** Reads a misc. register, including any side-effects the
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 7ace2204a..6e8b4a8c8 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -367,7 +367,7 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
     Addr nextInstAddr() { return thread->nextInstAddr(); }
     MicroPC microPC() { return thread->microPC(); }
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     {
         return thread->readMiscRegNoEffect(misc_reg);
     }
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 1f9e58ad9..e862385c5 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -372,7 +372,7 @@ class SimpleThread : public ThreadState
     }
 
     MiscReg
-    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
+    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
     {
         return isa->readMiscRegNoEffect(misc_reg);
     }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 850ff9468..966924c50 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -225,7 +225,7 @@ class ThreadContext
 
     virtual MicroPC microPC() = 0;
 
-    virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
+    virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
 
     virtual MiscReg readMiscReg(int misc_reg) = 0;
 
@@ -429,7 +429,7 @@ class ProxyThreadContext : public ThreadContext
     void setPredicate(bool val)
     { actualTC->setPredicate(val); }
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     { return actualTC->readMiscRegNoEffect(misc_reg); }
 
     MiscReg readMiscReg(int misc_reg)