Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.

src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
    Change ExecContext to ThreadContext.

--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e

48 files changed, 704 insertions, 688 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index e48edb2a8..d77f03126 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -39,7 +39,7 @@
 #include "base/output.hh"
 #include "cpu/base.hh"
 #include "cpu/cpuevent.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/profile.hh"
 #include "cpu/sampler/sampler.hh"
 #include "sim/param.hh"
@@ -179,7 +179,7 @@ void
 BaseCPU::init()
 {
     if (!params->deferRegistration)
-        registerExecContexts();
+        registerThreadContexts();
 }
 
 void
@@ -202,15 +202,15 @@ BaseCPU::regStats()
         .desc("number of cpu cycles simulated")
         ;
 
-    int size = execContexts.size();
+    int size = threadContexts.size();
     if (size > 1) {
         for (int i = 0; i < size; ++i) {
             stringstream namestr;
             ccprintf(namestr, "%s.ctx%d", name(), i);
-            execContexts[i]->regStats(namestr.str());
+            threadContexts[i]->regStats(namestr.str());
         }
     } else if (size == 1)
-        execContexts[0]->regStats(name());
+        threadContexts[0]->regStats(name());
 
 #if FULL_SYSTEM
 #endif
@@ -218,19 +218,19 @@ BaseCPU::regStats()
 
 
 void
-BaseCPU::registerExecContexts()
+BaseCPU::registerThreadContexts()
 {
-    for (int i = 0; i < execContexts.size(); ++i) {
-        ExecContext *xc = execContexts[i];
+    for (int i = 0; i < threadContexts.size(); ++i) {
+        ThreadContext *tc = threadContexts[i];
 
 #if FULL_SYSTEM
         int id = params->cpu_id;
         if (id != -1)
             id += i;
 
-        xc->setCpuId(system->registerExecContext(xc, id));
+        tc->setCpuId(system->registerThreadContext(tc, id));
 #else
-        xc->setCpuId(xc->getProcessPtr()->registerExecContext(xc));
+        tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc));
 #endif
     }
 }
@@ -245,22 +245,22 @@ BaseCPU::switchOut(Sampler *sampler)
 void
 BaseCPU::takeOverFrom(BaseCPU *oldCPU)
 {
-    assert(execContexts.size() == oldCPU->execContexts.size());
+    assert(threadContexts.size() == oldCPU->threadContexts.size());
 
-    for (int i = 0; i < execContexts.size(); ++i) {
-        ExecContext *newXC = execContexts[i];
-        ExecContext *oldXC = oldCPU->execContexts[i];
+    for (int i = 0; i < threadContexts.size(); ++i) {
+        ThreadContext *newTC = threadContexts[i];
+        ThreadContext *oldTC = oldCPU->threadContexts[i];
 
-        newXC->takeOverFrom(oldXC);
+        newTC->takeOverFrom(oldTC);
 
-        CpuEvent::replaceExecContext(oldXC, newXC);
+        CpuEvent::replaceThreadContext(oldTC, newTC);
 
-        assert(newXC->readCpuId() == oldXC->readCpuId());
+        assert(newTC->readCpuId() == oldTC->readCpuId());
 #if FULL_SYSTEM
-        system->replaceExecContext(newXC, newXC->readCpuId());
+        system->replaceThreadContext(newTC, newTC->readCpuId());
 #else
-        assert(newXC->getProcessPtr() == oldXC->getProcessPtr());
-        newXC->getProcessPtr()->replaceExecContext(newXC, newXC->readCpuId());
+        assert(newTC->getProcessPtr() == oldTC->getProcessPtr());
+        newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId());
 #endif
     }
 
@@ -269,8 +269,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
         interrupts[i] = oldCPU->interrupts[i];
     intstatus = oldCPU->intstatus;
 
-    for (int i = 0; i < execContexts.size(); ++i)
-        execContexts[i]->profileClear();
+    for (int i = 0; i < threadContexts.size(); ++i)
+        threadContexts[i]->profileClear();
 
     if (profileEvent)
         profileEvent->schedule(curTick);
@@ -286,9 +286,9 @@ BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval)
 void
 BaseCPU::ProfileEvent::process()
 {
-    for (int i = 0, size = cpu->execContexts.size(); i < size; ++i) {
-        ExecContext *xc = cpu->execContexts[i];
-        xc->profileSample();
+    for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) {
+        ThreadContext *tc = cpu->threadContexts[i];
+        tc->profileSample();
     }
 
     schedule(curTick + interval);
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index c28812b61..43122f238 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -43,7 +43,7 @@
 
 class BranchPred;
 class CheckerCPU;
-class ExecContext;
+class ThreadContext;
 class System;
 
 class BaseCPU : public SimObject
@@ -92,7 +92,7 @@ class BaseCPU : public SimObject
 #endif
 
   protected:
-    std::vector<ExecContext *> execContexts;
+    std::vector<ThreadContext *> threadContexts;
 
   public:
 
@@ -144,7 +144,7 @@ class BaseCPU : public SimObject
 
     virtual void activateWhenReady(int tid) {};
 
-    void registerExecContexts();
+    void registerThreadContexts();
 
     /// Prepare for another CPU to take over execution.  When it is
     /// is ready (drained pipe) it signals the sampler.
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 1f2b44e02..0657be324 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -193,7 +193,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Pointer to the FullCPU object. */
     FullCPU *cpu;
 
-    /** Pointer to the exec context. */
+    /** Pointer to the thread state. */
     ImplState *thread;
 
     /** The kind of fault this instruction has generated. */
@@ -587,10 +587,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
     void setState(ImplState *state) { thread = state; }
 
-    /** Returns the exec context.
-     *  @todo: Remove this once the ExecContext is no longer used.
+    /** Returns the thread context.
      */
-    ExecContext *xcBase() { return thread->getXCProxy(); }
+    ThreadContext *tcBase() { return thread->getTC(); }
 
   private:
     /** Instruction effective address.
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index c94570d7d..7ae7047e8 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -34,7 +34,7 @@
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/static_inst.hh"
 #include "sim/byteswap.hh"
 #include "sim/sim_object.hh"
@@ -62,7 +62,7 @@ CheckerCPU::init()
 }
 
 CheckerCPU::CheckerCPU(Params *p)
-    : BaseCPU(p), cpuXC(NULL), xcProxy(NULL)
+    : BaseCPU(p), cpuXC(NULL), tc(NULL)
 {
     memReq = NULL;
 
@@ -97,17 +97,16 @@ CheckerCPU::setMemory(MemObject *mem)
     cpuXC = new CPUExecContext(this, /* thread_num */ 0, process,
                                /* asid */ 0, mem);
 
-    cpuXC->setStatus(ExecContext::Suspended);
-    xcProxy = cpuXC->getProxy();
-    execContexts.push_back(xcProxy);
+    cpuXC->setStatus(ThreadContext::Suspended);
+    tc = cpuXC->getTC();
+    threadContexts.push_back(tc);
 #else
     if (systemPtr) {
         cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
 
-        cpuXC->setStatus(ExecContext::Suspended);
-        xcProxy = cpuXC->getProxy();
-        execContexts.push_back(xcProxy);
-        memReq->xc = xcProxy;
+        cpuXC->setStatus(ThreadContext::Suspended);
+        tc = cpuXC->getTC();
+        threadContexts.push_back(tc);
         delete cpuXC->kernelStats;
         cpuXC->kernelStats = NULL;
     }
@@ -123,10 +122,9 @@ CheckerCPU::setSystem(System *system)
     if (memPtr) {
         cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
 
-        cpuXC->setStatus(ExecContext::Suspended);
-        xcProxy = cpuXC->getProxy();
-        execContexts.push_back(xcProxy);
-        memReq->xc = xcProxy;
+        cpuXC->setStatus(ThreadContext::Suspended);
+        tc = cpuXC->getTC();
+        threadContexts.push_back(tc);
         delete cpuXC->kernelStats;
         cpuXC->kernelStats = NULL;
     }
@@ -742,12 +740,12 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
         int misc_reg_idx = miscRegIdxs.front();
         miscRegIdxs.pop();
 
-        if (inst->xcBase()->readMiscReg(misc_reg_idx) !=
+        if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
             cpuXC->readMiscReg(misc_reg_idx)) {
             warn("%lli: Misc reg idx %i (side effect) does not match! "
                  "Inst: %#x, checker: %#x",
                  curTick, misc_reg_idx,
-                 inst->xcBase()->readMiscReg(misc_reg_idx),
+                 inst->tcBase()->readMiscReg(misc_reg_idx),
                  cpuXC->readMiscReg(misc_reg_idx));
             handleError();
         }
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 704580d80..484f4cf04 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -60,7 +60,7 @@ class Process;
 #endif // FULL_SYSTEM
 template <class>
 class BaseDynInst;
-class ExecContext;
+class ThreadContext;
 class MemInterface;
 class Checkpoint;
 class Request;
@@ -76,11 +76,11 @@ class Sampler;
  * the values of uncached accesses.  In these cases, and with
  * instructions marked as "IsUnverifiable", the checker assumes that
  * the value from the main CPU's execution is correct and simply
- * copies that value.  It provides a CheckerExecContext (see
+ * copies that value.  It provides a CheckerThreadContext (see
  * checker/exec_context.hh) that provides hooks for updating the
- * Checker's state through any ExecContext accesses.  This allows the
+ * Checker's state through any ThreadContext accesses.  This allows the
  * checker to be able to correctly verify instructions, even with
- * external accesses to the ExecContext that change state.
+ * external accesses to the ThreadContext that change state.
  */
 class CheckerCPU : public BaseCPU
 {
@@ -132,7 +132,7 @@ class CheckerCPU : public BaseCPU
     // execution context
     CPUExecContext *cpuXC;
 
-    ExecContext *xcProxy;
+    ThreadContext *tc;
 
     AlphaITB *itb;
     AlphaDTB *dtb;
@@ -340,7 +340,7 @@ class CheckerCPU : public BaseCPU
     }
     bool checkFlags(Request *req);
 
-    ExecContext *xcBase() { return xcProxy; }
+    ThreadContext *tcBase() { return tc; }
     CPUExecContext *cpuXCBase() { return cpuXC; }
 
     Result unverifiedResult;
diff --git a/src/cpu/checker/exec_context.hh b/src/cpu/checker/exec_context.hh
index 054739a6a..48890584d 100644
--- a/src/cpu/checker/exec_context.hh
+++ b/src/cpu/checker/exec_context.hh
@@ -31,7 +31,7 @@
 
 #include "cpu/checker/cpu.hh"
 #include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 
 class EndQuiesceEvent;
 namespace Kernel {
@@ -39,251 +39,251 @@ namespace Kernel {
 };
 
 /**
- * Derived ExecContext class for use with the Checker.  The template
- * parameter is the ExecContext class used by the specific CPU being
- * verified.  This CheckerExecContext is then used by the main CPU in
- * place of its usual ExecContext class.  It handles updating the
- * checker's state any time state is updated through the ExecContext.
+ * Derived ThreadContext class for use with the Checker.  The template
+ * parameter is the ThreadContext class used by the specific CPU being
+ * verified.  This CheckerThreadContext is then used by the main CPU in
+ * place of its usual ThreadContext class.  It handles updating the
+ * checker's state any time state is updated through the ThreadContext.
  */
-template <class XC>
-class CheckerExecContext : public ExecContext
+template <class TC>
+class CheckerThreadContext : public ThreadContext
 {
   public:
-    CheckerExecContext(XC *actual_xc,
+    CheckerThreadContext(TC *actual_tc,
                        CheckerCPU *checker_cpu)
-        : actualXC(actual_xc), checkerXC(checker_cpu->cpuXC),
+        : actualTC(actual_tc), checkerTC(checker_cpu->cpuXC),
           checkerCPU(checker_cpu)
     { }
 
   private:
-    XC *actualXC;
-    CPUExecContext *checkerXC;
+    TC *actualTC;
+    CPUExecContext *checkerTC;
     CheckerCPU *checkerCPU;
 
   public:
 
-    BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
+    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 
     void setCpuId(int id)
     {
-        actualXC->setCpuId(id);
-        checkerXC->setCpuId(id);
+        actualTC->setCpuId(id);
+        checkerTC->setCpuId(id);
     }
 
-    int readCpuId() { return actualXC->readCpuId(); }
+    int readCpuId() { return actualTC->readCpuId(); }
 
-    TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
+    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
 
 #if FULL_SYSTEM
-    System *getSystemPtr() { return actualXC->getSystemPtr(); }
+    System *getSystemPtr() { return actualTC->getSystemPtr(); }
 
-    PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); }
+    PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
 
-    AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
+    AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
 
-    AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
+    AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
-    Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); }
+    Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
 #else
-    Process *getProcessPtr() { return actualXC->getProcessPtr(); }
+    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 #endif
 
-    Status status() const { return actualXC->status(); }
+    Status status() const { return actualTC->status(); }
 
     void setStatus(Status new_status)
     {
-        actualXC->setStatus(new_status);
-        checkerXC->setStatus(new_status);
+        actualTC->setStatus(new_status);
+        checkerTC->setStatus(new_status);
     }
 
     /// Set the status to Active.  Optional delay indicates number of
     /// cycles to wait before beginning execution.
-    void activate(int delay = 1) { actualXC->activate(delay); }
+    void activate(int delay = 1) { actualTC->activate(delay); }
 
     /// Set the status to Suspended.
-    void suspend() { actualXC->suspend(); }
+    void suspend() { actualTC->suspend(); }
 
     /// Set the status to Unallocated.
-    void deallocate() { actualXC->deallocate(); }
+    void deallocate() { actualTC->deallocate(); }
 
     /// Set the status to Halted.
-    void halt() { actualXC->halt(); }
+    void halt() { actualTC->halt(); }
 
 #if FULL_SYSTEM
-    void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
+    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 #endif
 
-    void takeOverFrom(ExecContext *oldContext)
+    void takeOverFrom(ThreadContext *oldContext)
     {
-        actualXC->takeOverFrom(oldContext);
-        checkerXC->takeOverFrom(oldContext);
+        actualTC->takeOverFrom(oldContext);
+        checkerTC->takeOverFrom(oldContext);
     }
 
-    void regStats(const std::string &name) { actualXC->regStats(name); }
+    void regStats(const std::string &name) { actualTC->regStats(name); }
 
-    void serialize(std::ostream &os) { actualXC->serialize(os); }
+    void serialize(std::ostream &os) { actualTC->serialize(os); }
     void unserialize(Checkpoint *cp, const std::string &section)
-    { actualXC->unserialize(cp, section); }
+    { actualTC->unserialize(cp, section); }
 
 #if FULL_SYSTEM
-    EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
+    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 
-    Tick readLastActivate() { return actualXC->readLastActivate(); }
-    Tick readLastSuspend() { return actualXC->readLastSuspend(); }
+    Tick readLastActivate() { return actualTC->readLastActivate(); }
+    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 
-    void profileClear() { return actualXC->profileClear(); }
-    void profileSample() { return actualXC->profileSample(); }
+    void profileClear() { return actualTC->profileClear(); }
+    void profileSample() { return actualTC->profileSample(); }
 #endif
 
-    int getThreadNum() { return actualXC->getThreadNum(); }
+    int getThreadNum() { return actualTC->getThreadNum(); }
 
     // @todo: Do I need this?
-    MachInst getInst() { return actualXC->getInst(); }
+    MachInst getInst() { return actualTC->getInst(); }
 
     // @todo: Do I need this?
-    void copyArchRegs(ExecContext *xc)
+    void copyArchRegs(ThreadContext *tc)
     {
-        actualXC->copyArchRegs(xc);
-        checkerXC->copyArchRegs(xc);
+        actualTC->copyArchRegs(tc);
+        checkerTC->copyArchRegs(tc);
     }
 
     void clearArchRegs()
     {
-        actualXC->clearArchRegs();
-        checkerXC->clearArchRegs();
+        actualTC->clearArchRegs();
+        checkerTC->clearArchRegs();
     }
 
     //
     // New accessors for new decoder.
     //
     uint64_t readIntReg(int reg_idx)
-    { return actualXC->readIntReg(reg_idx); }
+    { return actualTC->readIntReg(reg_idx); }
 
     FloatReg readFloatReg(int reg_idx, int width)
-    { return actualXC->readFloatReg(reg_idx, width); }
+    { return actualTC->readFloatReg(reg_idx, width); }
 
     FloatReg readFloatReg(int reg_idx)
-    { return actualXC->readFloatReg(reg_idx); }
+    { return actualTC->readFloatReg(reg_idx); }
 
     FloatRegBits readFloatRegBits(int reg_idx, int width)
-    { return actualXC->readFloatRegBits(reg_idx, width); }
+    { return actualTC->readFloatRegBits(reg_idx, width); }
 
     FloatRegBits readFloatRegBits(int reg_idx)
-    { return actualXC->readFloatRegBits(reg_idx); }
+    { return actualTC->readFloatRegBits(reg_idx); }
 
     void setIntReg(int reg_idx, uint64_t val)
     {
-        actualXC->setIntReg(reg_idx, val);
-        checkerXC->setIntReg(reg_idx, val);
+        actualTC->setIntReg(reg_idx, val);
+        checkerTC->setIntReg(reg_idx, val);
     }
 
     void setFloatReg(int reg_idx, FloatReg val, int width)
     {
-        actualXC->setFloatReg(reg_idx, val, width);
-        checkerXC->setFloatReg(reg_idx, val, width);
+        actualTC->setFloatReg(reg_idx, val, width);
+        checkerTC->setFloatReg(reg_idx, val, width);
     }
 
     void setFloatReg(int reg_idx, FloatReg val)
     {
-        actualXC->setFloatReg(reg_idx, val);
-        checkerXC->setFloatReg(reg_idx, val);
+        actualTC->setFloatReg(reg_idx, val);
+        checkerTC->setFloatReg(reg_idx, val);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
     {
-        actualXC->setFloatRegBits(reg_idx, val, width);
-        checkerXC->setFloatRegBits(reg_idx, val, width);
+        actualTC->setFloatRegBits(reg_idx, val, width);
+        checkerTC->setFloatRegBits(reg_idx, val, width);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
-        actualXC->setFloatRegBits(reg_idx, val);
-        checkerXC->setFloatRegBits(reg_idx, val);
+        actualTC->setFloatRegBits(reg_idx, val);
+        checkerTC->setFloatRegBits(reg_idx, val);
     }
 
-    uint64_t readPC() { return actualXC->readPC(); }
+    uint64_t readPC() { return actualTC->readPC(); }
 
     void setPC(uint64_t val)
     {
-        actualXC->setPC(val);
-        checkerXC->setPC(val);
+        actualTC->setPC(val);
+        checkerTC->setPC(val);
         checkerCPU->recordPCChange(val);
     }
 
-    uint64_t readNextPC() { return actualXC->readNextPC(); }
+    uint64_t readNextPC() { return actualTC->readNextPC(); }
 
     void setNextPC(uint64_t val)
     {
-        actualXC->setNextPC(val);
-        checkerXC->setNextPC(val);
+        actualTC->setNextPC(val);
+        checkerTC->setNextPC(val);
         checkerCPU->recordNextPCChange(val);
     }
 
-    uint64_t readNextNPC() { return actualXC->readNextNPC(); }
+    uint64_t readNextNPC() { return actualTC->readNextNPC(); }
 
     void setNextNPC(uint64_t val)
     {
-        actualXC->setNextNPC(val);
-        checkerXC->setNextNPC(val);
+        actualTC->setNextNPC(val);
+        checkerTC->setNextNPC(val);
         checkerCPU->recordNextPCChange(val);
     }
 
     MiscReg readMiscReg(int misc_reg)
-    { return actualXC->readMiscReg(misc_reg); }
+    { return actualTC->readMiscReg(misc_reg); }
 
     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
-    { return actualXC->readMiscRegWithEffect(misc_reg, fault); }
+    { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
 
     Fault setMiscReg(int misc_reg, const MiscReg &val)
     {
-        checkerXC->setMiscReg(misc_reg, val);
-        return actualXC->setMiscReg(misc_reg, val);
+        checkerTC->setMiscReg(misc_reg, val);
+        return actualTC->setMiscReg(misc_reg, val);
     }
 
     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
-        checkerXC->setMiscRegWithEffect(misc_reg, val);
-        return actualXC->setMiscRegWithEffect(misc_reg, val);
+        checkerTC->setMiscRegWithEffect(misc_reg, val);
+        return actualTC->setMiscRegWithEffect(misc_reg, val);
     }
 
     unsigned readStCondFailures()
-    { return actualXC->readStCondFailures(); }
+    { return actualTC->readStCondFailures(); }
 
     void setStCondFailures(unsigned sc_failures)
     {
-        checkerXC->setStCondFailures(sc_failures);
-        actualXC->setStCondFailures(sc_failures);
+        checkerTC->setStCondFailures(sc_failures);
+        actualTC->setStCondFailures(sc_failures);
     }
 #if FULL_SYSTEM
-    bool inPalMode() { return actualXC->inPalMode(); }
+    bool inPalMode() { return actualTC->inPalMode(); }
 #endif
 
     // @todo: Fix this!
-    bool misspeculating() { return actualXC->misspeculating(); }
+    bool misspeculating() { return actualTC->misspeculating(); }
 
 #if !FULL_SYSTEM
-    IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
+    IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, IntReg val)
     {
-        checkerXC->setSyscallArg(i, val);
-        actualXC->setSyscallArg(i, val);
+        checkerTC->setSyscallArg(i, val);
+        actualTC->setSyscallArg(i, val);
     }
 
     void setSyscallReturn(SyscallReturn return_value)
     {
-        checkerXC->setSyscallReturn(return_value);
-        actualXC->setSyscallReturn(return_value);
+        checkerTC->setSyscallReturn(return_value);
+        actualTC->setSyscallReturn(return_value);
     }
 
-    Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
+    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 #endif
     void changeRegFileContext(RegFile::ContextParam param,
             RegFile::ContextVal val)
     {
-        actualXC->changeRegFileContext(param, val);
-        checkerXC->changeRegFileContext(param, val);
+        actualTC->changeRegFileContext(param, val);
+        checkerTC->changeRegFileContext(param, val);
     }
 };
 
diff --git a/src/cpu/cpu_exec_context.cc b/src/cpu/cpu_exec_context.cc
index 1227d52f5..1e8071ca8 100644
--- a/src/cpu/cpu_exec_context.cc
+++ b/src/cpu/cpu_exec_context.cc
@@ -36,7 +36,7 @@
 #include "arch/isa_traits.hh"
 #include "cpu/base.hh"
 #include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 
 #if FULL_SYSTEM
 #include "base/callback.hh"
@@ -62,14 +62,14 @@ using namespace std;
 CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
                                AlphaITB *_itb, AlphaDTB *_dtb,
                                bool use_kernel_stats)
-    : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
+    : _status(ThreadContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
       cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb),
       dtb(_dtb), profile(NULL), func_exe_inst(0), storeCondFailures(0)
 
 {
-    proxy = new ProxyExecContext<CPUExecContext>(this);
+    tc = new ProxyThreadContext<CPUExecContext>(this);
 
-    quiesceEvent = new EndQuiesceEvent(proxy);
+    quiesceEvent = new EndQuiesceEvent(tc);
 
     regs.clear();
 
@@ -109,7 +109,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
 #else
 CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
                          Process *_process, int _asid, MemObject* memobj)
-    : _status(ExecContext::Unallocated),
+    : _status(ThreadContext::Unallocated),
       cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0),
       lastSuspend(0), process(_process), asid(_asid),
       func_exe_inst(0), storeCondFailures(0)
@@ -124,7 +124,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
     port->setPeer(mem_port);
 
     regs.clear();
-    proxy = new ProxyExecContext<CPUExecContext>(this);
+    tc = new ProxyThreadContext<CPUExecContext>(this);
 }
 
 CPUExecContext::CPUExecContext(RegFile *regFile)
@@ -132,14 +132,14 @@ CPUExecContext::CPUExecContext(RegFile *regFile)
       func_exe_inst(0), storeCondFailures(0)
 {
     regs = *regFile;
-    proxy = new ProxyExecContext<CPUExecContext>(this);
+    tc = new ProxyThreadContext<CPUExecContext>(this);
 }
 
 #endif
 
 CPUExecContext::~CPUExecContext()
 {
-    delete proxy;
+    delete tc;
 }
 
 #if FULL_SYSTEM
@@ -147,7 +147,7 @@ void
 CPUExecContext::dumpFuncProfile()
 {
     std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
-    profile->dump(proxy, *os);
+    profile->dump(tc, *os);
 }
 
 void
@@ -167,7 +167,7 @@ CPUExecContext::profileSample()
 #endif
 
 void
-CPUExecContext::takeOverFrom(ExecContext *oldContext)
+CPUExecContext::takeOverFrom(ThreadContext *oldContext)
 {
     // some things should already be set up
 #if FULL_SYSTEM
@@ -185,18 +185,18 @@ CPUExecContext::takeOverFrom(ExecContext *oldContext)
 #else
     EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
     if (quiesce) {
-        // Point the quiesce event's XC at this XC so that it wakes up
+        // Point the quiesce event's TC at this TC so that it wakes up
         // the proper CPU.
-        quiesce->xc = proxy;
+        quiesce->tc = tc;
     }
     if (quiesceEvent) {
-        quiesceEvent->xc = proxy;
+        quiesceEvent->tc = tc;
     }
 #endif
 
     storeCondFailures = 0;
 
-    oldContext->setStatus(ExecContext::Unallocated);
+    oldContext->setStatus(ThreadContext::Unallocated);
 }
 
 void
@@ -242,17 +242,17 @@ CPUExecContext::unserialize(Checkpoint *cp, const std::string &section)
 void
 CPUExecContext::activate(int delay)
 {
-    if (status() == ExecContext::Active)
+    if (status() == ThreadContext::Active)
         return;
 
     lastActivate = curTick;
 
-    if (status() == ExecContext::Unallocated) {
+    if (status() == ThreadContext::Unallocated) {
         cpu->activateWhenReady(thread_num);
         return;
     }
 
-    _status = ExecContext::Active;
+    _status = ThreadContext::Active;
 
     // status() == Suspended
     cpu->activateContext(thread_num, delay);
@@ -261,7 +261,7 @@ CPUExecContext::activate(int delay)
 void
 CPUExecContext::suspend()
 {
-    if (status() == ExecContext::Suspended)
+    if (status() == ThreadContext::Suspended)
         return;
 
     lastActivate = curTick;
@@ -270,32 +270,32 @@ CPUExecContext::suspend()
 #if FULL_SYSTEM
     // Don't change the status from active if there are pending interrupts
     if (cpu->check_interrupts()) {
-        assert(status() == ExecContext::Active);
+        assert(status() == ThreadContext::Active);
         return;
     }
 #endif
 */
-    _status = ExecContext::Suspended;
+    _status = ThreadContext::Suspended;
     cpu->suspendContext(thread_num);
 }
 
 void
 CPUExecContext::deallocate()
 {
-    if (status() == ExecContext::Unallocated)
+    if (status() == ThreadContext::Unallocated)
         return;
 
-    _status = ExecContext::Unallocated;
+    _status = ThreadContext::Unallocated;
     cpu->deallocateContext(thread_num);
 }
 
 void
 CPUExecContext::halt()
 {
-    if (status() == ExecContext::Halted)
+    if (status() == ThreadContext::Halted)
         return;
 
-    _status = ExecContext::Halted;
+    _status = ThreadContext::Halted;
     cpu->haltContext(thread_num);
 }
 
@@ -310,22 +310,22 @@ CPUExecContext::regStats(const string &name)
 }
 
 void
-CPUExecContext::copyArchRegs(ExecContext *xc)
+CPUExecContext::copyArchRegs(ThreadContext *src_tc)
 {
-    TheISA::copyRegs(xc, proxy);
+    TheISA::copyRegs(src_tc, tc);
 }
 
 #if FULL_SYSTEM
 VirtualPort*
-CPUExecContext::getVirtPort(ExecContext *xc)
+CPUExecContext::getVirtPort(ThreadContext *src_tc)
 {
-    if (!xc)
+    if (!src_tc)
         return virtPort;
 
     VirtualPort *vp;
     Port *mem_port;
 
-    vp = new VirtualPort("xc-vport", xc);
+    vp = new VirtualPort("tc-vport", src_tc);
     mem_port = system->physmem->getPort("functional");
     mem_port->setPeer(vp);
     vp->setPeer(mem_port);
@@ -335,7 +335,7 @@ CPUExecContext::getVirtPort(ExecContext *xc)
 void
 CPUExecContext::delVirtPort(VirtualPort *vp)
 {
-//    assert(!vp->nullExecContext());
+//    assert(!vp->nullThreadContext());
     delete vp->getPeer();
     delete vp;
 }
diff --git a/src/cpu/cpu_exec_context.hh b/src/cpu/cpu_exec_context.hh
index 5faa8d19c..01b5cbb15 100644
--- a/src/cpu/cpu_exec_context.hh
+++ b/src/cpu/cpu_exec_context.hh
@@ -34,7 +34,7 @@
 
 #include "arch/isa_traits.hh"
 #include "config/full_system.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "mem/physical.hh"
 #include "mem/request.hh"
 #include "sim/byteswap.hh"
@@ -84,7 +84,7 @@ class CPUExecContext
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
   public:
-    typedef ExecContext::Status Status;
+    typedef ThreadContext::Status Status;
 
   private:
     Status _status;
@@ -114,7 +114,7 @@ class CPUExecContext
     // pointer to CPU associated with this context
     BaseCPU *cpu;
 
-    ProxyExecContext<CPUExecContext> *proxy;
+    ProxyThreadContext<CPUExecContext> *tc;
 
     // Current instruction
     MachInst inst;
@@ -215,7 +215,7 @@ class CPUExecContext
 #endif
     virtual ~CPUExecContext();
 
-    virtual void takeOverFrom(ExecContext *oldContext);
+    virtual void takeOverFrom(ThreadContext *oldContext);
 
     void regStats(const std::string &name);
 
@@ -224,7 +224,7 @@ class CPUExecContext
 
     BaseCPU *getCpuPtr() { return cpu; }
 
-    ExecContext *getProxy() { return proxy; }
+    ThreadContext *getTC() { return tc; }
 
     int getThreadNum() { return thread_num; }
 
@@ -240,25 +240,25 @@ class CPUExecContext
 
     Fault translateInstReq(RequestPtr &req)
     {
-        return itb->translate(req, proxy);
+        return itb->translate(req, tc);
     }
 
     Fault translateDataReadReq(RequestPtr &req)
     {
-        return dtb->translate(req, proxy, false);
+        return dtb->translate(req, tc, false);
     }
 
     Fault translateDataWriteReq(RequestPtr &req)
     {
-        return dtb->translate(req, proxy, true);
+        return dtb->translate(req, tc, true);
     }
 
     FunctionalPort *getPhysPort() { return physPort; }
 
-    /** Return a virtual port. If no exec context is specified then a static
+    /** Return a virtual port. If no thread context is specified then a static
      * port is returned. Otherwise a port is created and returned. It must be
      * deleted by deleteVirtPort(). */
-    VirtualPort *getVirtPort(ExecContext *xc);
+    VirtualPort *getVirtPort(ThreadContext *tc);
 
     void delVirtPort(VirtualPort *vp);
 
@@ -377,7 +377,7 @@ class CPUExecContext
 
     int readCpuId() { return cpu_id; }
 
-    void copyArchRegs(ExecContext *xc);
+    void copyArchRegs(ThreadContext *tc);
 
     //
     // New accessors for new decoder.
@@ -470,7 +470,7 @@ class CPUExecContext
 
     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
     {
-        return regs.readMiscRegWithEffect(misc_reg, fault, proxy);
+        return regs.readMiscRegWithEffect(misc_reg, fault, tc);
     }
 
     Fault setMiscReg(int misc_reg, const MiscReg &val)
@@ -480,7 +480,7 @@ class CPUExecContext
 
     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
-        return regs.setMiscRegWithEffect(misc_reg, val, proxy);
+        return regs.setMiscRegWithEffect(misc_reg, val, tc);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }
@@ -517,7 +517,7 @@ class CPUExecContext
 
     void syscall(int64_t callnum)
     {
-        process->syscall(callnum, proxy);
+        process->syscall(callnum, tc);
     }
 
     Counter readFuncExeInst() { return func_exe_inst; }
diff --git a/src/cpu/cpuevent.cc b/src/cpu/cpuevent.cc
index ae1dd7fa3..679244a6b 100644
--- a/src/cpu/cpuevent.cc
+++ b/src/cpu/cpuevent.cc
@@ -30,7 +30,7 @@
 
 #include "cpu/cpuevent.hh"
 
-/** Static list of all CpuEvent objects so we can modify their execution
+/** Static list of all CpuEvent objects so we can modify their thread
  * contexts as needed. */
 CpuEvent::CpuEventList CpuEvent::cpuEventList;
 
@@ -48,14 +48,14 @@ CpuEvent::~CpuEvent()
 }
 
 void
-CpuEvent::replaceExecContext(ExecContext *oldXc, ExecContext *newXc)
+CpuEvent::replaceThreadContext(ThreadContext *oldTc, ThreadContext *newTc)
 {
     CpuEventList::iterator i;
 
-    // Update any events that have the old execution context with the new exec
+    // Update any events that have the old thread context with the new thread
     // context
     for (i = cpuEventList.begin(); i != cpuEventList.end(); i++) {
-        if ((*i)->xc == oldXc)
-            (*i)->xc = newXc;
+        if ((*i)->tc == oldTc)
+            (*i)->tc = newTc;
     }
 }
diff --git a/src/cpu/cpuevent.hh b/src/cpu/cpuevent.hh
index 10359b121..11ac7aafb 100644
--- a/src/cpu/cpuevent.hh
+++ b/src/cpu/cpuevent.hh
@@ -34,11 +34,11 @@
 #include <vector>
 #include "sim/eventq.hh"
 
-class ExecContext;
+class ThreadContext;
 
 /** This class creates a global list of events than need a pointer to an
- * execution context. When a switchover takes place the events can be migrated
- * to the new execution context, otherwise you could have a wake timer interrupt
+ * thread context. When a switchover takes place the events can be migrated
+ * to the new thread context, otherwise you could have a wake timer interrupt
  * go off on a switched out cpu or other unfortunate events. This object MUST be
  * dynamically allocated to avoid it being deleted after a cpu switch happens.
  * */
@@ -52,36 +52,37 @@ class CpuEvent : public Event
      * happens. */
     static CpuEventList cpuEventList;
 
-    /** The execution context that is switched to the new cpus. */
-    ExecContext *xc;
+    /** The thread context that is switched to the new cpus. */
+    ThreadContext *tc;
 
   public:
-    CpuEvent(EventQueue *q, ExecContext *_xc, Priority p = Default_Pri)
-        : Event(q, p), xc(_xc)
+    CpuEvent(EventQueue *q, ThreadContext *_tc, Priority p = Default_Pri)
+        : Event(q, p), tc(_tc)
     { cpuEventList.push_back(this); }
 
     /** delete the cpu event from the global list. */
     ~CpuEvent();
 
-    /** Update all events switching old xc to new xc.
-     * @param oldXc the old exeuction context we are switching from
-     * @param newXc the new execution context we are switching to.
+    /** Update all events switching old tc to new tc.
+     * @param oldTc the old thread context we are switching from
+     * @param newTc the new thread context we are switching to.
      */
-    static void replaceExecContext(ExecContext *oldXc, ExecContext *newXc);
+    static void replaceThreadContext(ThreadContext *oldTc,
+                                     ThreadContext *newTc);
 };
 
-template <class T, void (T::* F)(ExecContext *xc)>
+template <class T, void (T::* F)(ThreadContext *tc)>
 class CpuEventWrapper : public CpuEvent
 {
   private:
     T *object;
 
   public:
-    CpuEventWrapper(T *obj, ExecContext *_xc, EventQueue *q = &mainEventQueue,
+    CpuEventWrapper(T *obj, ThreadContext *_tc, EventQueue *q = &mainEventQueue,
             Priority p = Default_Pri)
-        : CpuEvent(q, _xc, p), object(obj)
+        : CpuEvent(q, _tc, p), object(obj)
     { }
-    void process() { (object->*F)(xc); }
+    void process() { (object->*F)(tc); }
 };
 
 #endif // __CPU_CPUEVENT_HH__
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index d31e99c4a..95f8b449c 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -38,7 +38,7 @@
 #include "sim/host.hh"
 #include "cpu/inst_seq.hh"	// for InstSeqNum
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/static_inst.hh"
 
 class BaseCPU;
@@ -173,14 +173,14 @@ InstRecord::setRegs(const IntRegFile &regs)
 
 inline
 InstRecord *
-getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
+getInstRecord(Tick cycle, ThreadContext *tc, BaseCPU *cpu,
               const StaticInstPtr staticInst,
               Addr pc, int thread = 0)
 {
     if (DTRACE(InstExec) &&
-        (InstRecord::traceMisspec() || !xc->misspeculating())) {
+        (InstRecord::traceMisspec() || !tc->misspeculating())) {
         return new InstRecord(cycle, cpu, staticInst, pc,
-                              xc->misspeculating(), thread);
+                              tc->misspeculating(), thread);
     }
 
     return NULL;
diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc
index 3171a352f..4cbc86891 100644
--- a/src/cpu/intr_control.cc
+++ b/src/cpu/intr_control.cc
@@ -33,7 +33,7 @@
 #include <vector>
 
 #include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/intr_control.hh"
 #include "sim/builder.hh"
 #include "sim/sim_object.hh"
@@ -51,32 +51,32 @@ IntrControl::IntrControl(const string &name, BaseCPU *c)
 void
 IntrControl::post(int int_num, int index)
 {
-    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
-    BaseCPU *temp = xcvec[0]->getCpuPtr();
+    std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+    BaseCPU *temp = tcvec[0]->getCpuPtr();
     temp->post_interrupt(int_num, index);
 }
 
 void
 IntrControl::post(int cpu_id, int int_num, int index)
 {
-    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
-    BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
+    std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+    BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
     temp->post_interrupt(int_num, index);
 }
 
 void
 IntrControl::clear(int int_num, int index)
 {
-    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
-    BaseCPU *temp = xcvec[0]->getCpuPtr();
+    std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+    BaseCPU *temp = tcvec[0]->getCpuPtr();
     temp->clear_interrupt(int_num, index);
 }
 
 void
 IntrControl::clear(int cpu_id, int int_num, int index)
 {
-    std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
-    BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
+    std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+    BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
     temp->clear_interrupt(int_num, index);
 }
 
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 60b3c1335..9976000e9 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -42,7 +42,7 @@
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
 
-class ExecContext;
+class ThreadContext;
 class MemTest : public SimObject
 {
   public:
diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
index 3c16c3b2e..588b11724 100644
--- a/src/cpu/o3/alpha_cpu.hh
+++ b/src/cpu/o3/alpha_cpu.hh
@@ -32,7 +32,7 @@
 #define __CPU_O3_ALPHA_FULL_CPU_HH__
 
 #include "arch/isa_traits.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/o3/cpu.hh"
 #include "sim/byteswap.hh"
 
@@ -71,20 +71,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     AlphaFullCPU(Params *params);
 
     /**
-     * Derived ExecContext class for use with the AlphaFullCPU.  It
+     * Derived ThreadContext class for use with the AlphaFullCPU.  It
      * provides the interface for any external objects to access a
      * single thread's state and some general CPU state.  Any time
      * external objects try to update state through this interface,
      * the CPU will create an event to squash all in-flight
      * instructions in order to ensure state is maintained correctly.
      */
-    class AlphaXC : public ExecContext
+    class AlphaTC : public ThreadContext
     {
       public:
         /** Pointer to the CPU. */
         AlphaFullCPU<Impl> *cpu;
 
-        /** Pointer to the thread state that this XC corrseponds to. */
+        /** Pointer to the thread state that this TC corrseponds to. */
         O3ThreadState<Impl> *thread;
 
         /** Returns a pointer to this CPU. */
@@ -145,9 +145,9 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         virtual void dumpFuncProfile();
 #endif
         /** Takes over execution of a thread from another CPU. */
-        virtual void takeOverFrom(ExecContext *old_context);
+        virtual void takeOverFrom(ThreadContext *old_context);
 
-        /** Registers statistics associated with this XC. */
+        /** Registers statistics associated with this TC. */
         virtual void regStats(const std::string &name);
 
         /** Serializes state. */
@@ -177,8 +177,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
          */
         virtual TheISA::MachInst getInst();
 
-        /** Copies the architectural registers from another XC into this XC. */
-        virtual void copyArchRegs(ExecContext *xc);
+        /** Copies the architectural registers from another TC into this TC. */
+        virtual void copyArchRegs(ThreadContext *tc);
 
         /** Resets all architectural registers to 0. */
         virtual void clearArchRegs();
@@ -359,9 +359,9 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
     /** Initiates a squash of all in-flight instructions for a given
      * thread.  The source of the squash is an external update of
-     * state through the XC.
+     * state through the TC.
      */
-    void squashFromXC(unsigned tid);
+    void squashFromTC(unsigned tid);
 
 #if FULL_SYSTEM
     /** Posts an interrupt. */
diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh
index 7c136638d..7f3d91640 100644
--- a/src/cpu/o3/alpha_cpu_impl.hh
+++ b/src/cpu/o3/alpha_cpu_impl.hh
@@ -68,7 +68,7 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
         // SMT is not supported in FS mode yet.
         assert(this->numThreads == 1);
         this->thread[i] = new Thread(this, 0, params->mem);
-        this->thread[i]->setStatus(ExecContext::Suspended);
+        this->thread[i]->setStatus(ThreadContext::Suspended);
 #else
         if (i < params->workload.size()) {
             DPRINTF(FullCPU, "FullCPU: Workload[%i] process is %#x",
@@ -76,11 +76,11 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
             this->thread[i] = new Thread(this, i, params->workload[i],
                                          i, params->mem);
 
-            this->thread[i]->setStatus(ExecContext::Suspended);
+            this->thread[i]->setStatus(ThreadContext::Suspended);
             //usedTids[i] = true;
             //threadMap[i] = i;
         } else {
-            //Allocate Empty execution context so M5 can use later
+            //Allocate Empty thread so M5 can use later
             //when scheduling threads to CPU
             Process* dummy_proc = NULL;
 
@@ -89,35 +89,35 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
         }
 #endif // !FULL_SYSTEM
 
-        ExecContext *xc_proxy;
+        ThreadContext *tc;
 
-        // Setup the XC that will serve as the interface to the threads/CPU.
-        AlphaXC *alpha_xc = new AlphaXC;
+        // Setup the TC that will serve as the interface to the threads/CPU.
+        AlphaTC *alpha_tc = new AlphaTC;
 
-        // If we're using a checker, then the XC should be the
-        // CheckerExecContext.
+        // If we're using a checker, then the TC should be the
+        // CheckerThreadContext.
         if (params->checker) {
-            xc_proxy = new CheckerExecContext<AlphaXC>(
-                alpha_xc, this->checker);
+            tc = new CheckerThreadContext<AlphaTC>(
+                alpha_tc, this->checker);
         } else {
-            xc_proxy = alpha_xc;
+            tc = alpha_tc;
         }
 
-        alpha_xc->cpu = this;
-        alpha_xc->thread = this->thread[i];
+        alpha_tc->cpu = this;
+        alpha_tc->thread = this->thread[i];
 
 #if FULL_SYSTEM
         // Setup quiesce event.
         this->thread[i]->quiesceEvent =
-            new EndQuiesceEvent(xc_proxy);
+            new EndQuiesceEvent(tc);
         this->thread[i]->lastActivate = 0;
         this->thread[i]->lastSuspend = 0;
 #endif
-        // Give the thread the XC.
-        this->thread[i]->xcProxy = xc_proxy;
+        // Give the thread the TC.
+        this->thread[i]->tc = tc;
 
-        // Add the XC to the CPU's list of XC's.
-        this->execContexts.push_back(xc_proxy);
+        // Add the TC to the CPU's list of TC's.
+        this->threadContexts.push_back(tc);
     }
 
 
@@ -156,7 +156,7 @@ AlphaFullCPU<Impl>::regStats()
 #if FULL_SYSTEM
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::dumpFuncProfile()
+AlphaFullCPU<Impl>::AlphaTC::dumpFuncProfile()
 {
     // Currently not supported
 }
@@ -164,7 +164,7 @@ AlphaFullCPU<Impl>::AlphaXC::dumpFuncProfile()
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
+AlphaFullCPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
     assert(getMemPort() == old_context->getMemPort());
@@ -184,12 +184,12 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
 #else
     EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
     if (other_quiesce) {
-        // Point the quiesce event's XC at this XC so that it wakes up
+        // Point the quiesce event's TC at this TC so that it wakes up
         // the proper CPU.
-        other_quiesce->xc = this;
+        other_quiesce->tc = this;
     }
     if (thread->quiesceEvent) {
-        thread->quiesceEvent->xc = this;
+        thread->quiesceEvent->tc = this;
     }
 
     // Transfer kernel stats from one CPU to the other.
@@ -198,7 +198,7 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
     cpu->lockFlag = false;
 #endif
 
-    old_context->setStatus(ExecContext::Unallocated);
+    old_context->setStatus(ThreadContext::Unallocated);
 
     thread->inSyscall = false;
     thread->trapPending = false;
@@ -206,23 +206,23 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::activate(int delay)
+AlphaFullCPU<Impl>::AlphaTC::activate(int delay)
 {
-    DPRINTF(FullCPU, "Calling activate on AlphaXC\n");
+    DPRINTF(FullCPU, "Calling activate on AlphaTC\n");
 
-    if (thread->status() == ExecContext::Active)
+    if (thread->status() == ThreadContext::Active)
         return;
 
 #if FULL_SYSTEM
     thread->lastActivate = curTick;
 #endif
 
-    if (thread->status() == ExecContext::Unallocated) {
+    if (thread->status() == ThreadContext::Unallocated) {
         cpu->activateWhenReady(thread->tid);
         return;
     }
 
-    thread->setStatus(ExecContext::Active);
+    thread->setStatus(ThreadContext::Active);
 
     // status() == Suspended
     cpu->activateContext(thread->tid, delay);
@@ -230,11 +230,11 @@ AlphaFullCPU<Impl>::AlphaXC::activate(int delay)
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::suspend()
+AlphaFullCPU<Impl>::AlphaTC::suspend()
 {
-    DPRINTF(FullCPU, "Calling suspend on AlphaXC\n");
+    DPRINTF(FullCPU, "Calling suspend on AlphaTC\n");
 
-    if (thread->status() == ExecContext::Suspended)
+    if (thread->status() == ThreadContext::Suspended)
         return;
 
 #if FULL_SYSTEM
@@ -245,44 +245,44 @@ AlphaFullCPU<Impl>::AlphaXC::suspend()
 #if FULL_SYSTEM
     // Don't change the status from active if there are pending interrupts
     if (cpu->check_interrupts()) {
-        assert(status() == ExecContext::Active);
+        assert(status() == ThreadContext::Active);
         return;
     }
 #endif
 */
-    thread->setStatus(ExecContext::Suspended);
+    thread->setStatus(ThreadContext::Suspended);
     cpu->suspendContext(thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::deallocate()
+AlphaFullCPU<Impl>::AlphaTC::deallocate()
 {
-    DPRINTF(FullCPU, "Calling deallocate on AlphaXC\n");
+    DPRINTF(FullCPU, "Calling deallocate on AlphaTC\n");
 
-    if (thread->status() == ExecContext::Unallocated)
+    if (thread->status() == ThreadContext::Unallocated)
         return;
 
-    thread->setStatus(ExecContext::Unallocated);
+    thread->setStatus(ThreadContext::Unallocated);
     cpu->deallocateContext(thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::halt()
+AlphaFullCPU<Impl>::AlphaTC::halt()
 {
-    DPRINTF(FullCPU, "Calling halt on AlphaXC\n");
+    DPRINTF(FullCPU, "Calling halt on AlphaTC\n");
 
-    if (thread->status() == ExecContext::Halted)
+    if (thread->status() == ThreadContext::Halted)
         return;
 
-    thread->setStatus(ExecContext::Halted);
+    thread->setStatus(ThreadContext::Halted);
     cpu->haltContext(thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::regStats(const std::string &name)
+AlphaFullCPU<Impl>::AlphaTC::regStats(const std::string &name)
 {
 #if FULL_SYSTEM
     thread->kernelStats = new Kernel::Statistics(cpu->system);
@@ -292,7 +292,7 @@ AlphaFullCPU<Impl>::AlphaXC::regStats(const std::string &name)
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::serialize(std::ostream &os)
+AlphaFullCPU<Impl>::AlphaTC::serialize(std::ostream &os)
 {
 #if FULL_SYSTEM
     if (thread->kernelStats)
@@ -303,7 +303,7 @@ AlphaFullCPU<Impl>::AlphaXC::serialize(std::ostream &os)
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::unserialize(Checkpoint *cp, const std::string &section)
+AlphaFullCPU<Impl>::AlphaTC::unserialize(Checkpoint *cp, const std::string &section)
 {
 #if FULL_SYSTEM
     if (thread->kernelStats)
@@ -315,46 +315,46 @@ AlphaFullCPU<Impl>::AlphaXC::unserialize(Checkpoint *cp, const std::string &sect
 #if FULL_SYSTEM
 template <class Impl>
 EndQuiesceEvent *
-AlphaFullCPU<Impl>::AlphaXC::getQuiesceEvent()
+AlphaFullCPU<Impl>::AlphaTC::getQuiesceEvent()
 {
     return thread->quiesceEvent;
 }
 
 template <class Impl>
 Tick
-AlphaFullCPU<Impl>::AlphaXC::readLastActivate()
+AlphaFullCPU<Impl>::AlphaTC::readLastActivate()
 {
     return thread->lastActivate;
 }
 
 template <class Impl>
 Tick
-AlphaFullCPU<Impl>::AlphaXC::readLastSuspend()
+AlphaFullCPU<Impl>::AlphaTC::readLastSuspend()
 {
     return thread->lastSuspend;
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::profileClear()
+AlphaFullCPU<Impl>::AlphaTC::profileClear()
 {}
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::profileSample()
+AlphaFullCPU<Impl>::AlphaTC::profileSample()
 {}
 #endif
 
 template <class Impl>
 TheISA::MachInst
-AlphaFullCPU<Impl>::AlphaXC:: getInst()
+AlphaFullCPU<Impl>::AlphaTC:: getInst()
 {
     return thread->inst;
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::copyArchRegs(ExecContext *xc)
+AlphaFullCPU<Impl>::AlphaTC::copyArchRegs(ThreadContext *tc)
 {
     // This function will mess things up unless the ROB is empty and
     // there are no instructions in the pipeline.
@@ -368,44 +368,44 @@ AlphaFullCPU<Impl>::AlphaXC::copyArchRegs(ExecContext *xc)
         DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
                 "now has data %lli.\n",
                 renamed_reg, cpu->readIntReg(renamed_reg),
-                xc->readIntReg(i));
+                tc->readIntReg(i));
 
-        cpu->setIntReg(renamed_reg, xc->readIntReg(i));
+        cpu->setIntReg(renamed_reg, tc->readIntReg(i));
     }
 
     // Then loop through the floating point registers.
     for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) {
         renamed_reg = cpu->renameMap[tid].lookup(i + AlphaISA::FP_Base_DepTag);
         cpu->setFloatRegBits(renamed_reg,
-                             xc->readFloatRegBits(i));
+                             tc->readFloatRegBits(i));
     }
 
     // Copy the misc regs.
-    copyMiscRegs(xc, this);
+    copyMiscRegs(tc, this);
 
     // Then finally set the PC and the next PC.
-    cpu->setPC(xc->readPC(), tid);
-    cpu->setNextPC(xc->readNextPC(), tid);
+    cpu->setPC(tc->readPC(), tid);
+    cpu->setNextPC(tc->readNextPC(), tid);
 #if !FULL_SYSTEM
-    this->thread->funcExeInst = xc->readFuncExeInst();
+    this->thread->funcExeInst = tc->readFuncExeInst();
 #endif
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::clearArchRegs()
+AlphaFullCPU<Impl>::AlphaTC::clearArchRegs()
 {}
 
 template <class Impl>
 uint64_t
-AlphaFullCPU<Impl>::AlphaXC::readIntReg(int reg_idx)
+AlphaFullCPU<Impl>::AlphaTC::readIntReg(int reg_idx)
 {
     return cpu->readArchIntReg(reg_idx, thread->tid);
 }
 
 template <class Impl>
 FloatReg
-AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx, int width)
+AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx, int width)
 {
     switch(width) {
       case 32:
@@ -420,41 +420,41 @@ AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx, int width)
 
 template <class Impl>
 FloatReg
-AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx)
+AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx)
 {
     return cpu->readArchFloatRegSingle(reg_idx, thread->tid);
 }
 
 template <class Impl>
 FloatRegBits
-AlphaFullCPU<Impl>::AlphaXC::readFloatRegBits(int reg_idx, int width)
+AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx, int width)
 {
-    DPRINTF(Fault, "Reading floatint register through the XC!\n");
+    DPRINTF(Fault, "Reading floatint register through the TC!\n");
     return cpu->readArchFloatRegInt(reg_idx, thread->tid);
 }
 
 template <class Impl>
 FloatRegBits
-AlphaFullCPU<Impl>::AlphaXC::readFloatRegBits(int reg_idx)
+AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx)
 {
     return cpu->readArchFloatRegInt(reg_idx, thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setIntReg(int reg_idx, uint64_t val)
+AlphaFullCPU<Impl>::AlphaTC::setIntReg(int reg_idx, uint64_t val)
 {
     cpu->setArchIntReg(reg_idx, val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val, int width)
+AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width)
 {
     switch(width) {
       case 32:
@@ -467,80 +467,80 @@ AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val, int width)
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val)
+AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val)
 {
     cpu->setArchFloatRegSingle(reg_idx, val, thread->tid);
 
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setFloatRegBits(int reg_idx, FloatRegBits val,
+AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val,
                                              int width)
 {
-    DPRINTF(Fault, "Setting floatint register through the XC!\n");
+    DPRINTF(Fault, "Setting floatint register through the TC!\n");
     cpu->setArchFloatRegInt(reg_idx, val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setFloatRegBits(int reg_idx, FloatRegBits val)
+AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     cpu->setArchFloatRegInt(reg_idx, val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setPC(uint64_t val)
+AlphaFullCPU<Impl>::AlphaTC::setPC(uint64_t val)
 {
     cpu->setPC(val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setNextPC(uint64_t val)
+AlphaFullCPU<Impl>::AlphaTC::setNextPC(uint64_t val)
 {
     cpu->setNextPC(val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 }
 
 template <class Impl>
 Fault
-AlphaFullCPU<Impl>::AlphaXC::setMiscReg(int misc_reg, const MiscReg &val)
+AlphaFullCPU<Impl>::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val)
 {
     Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 
     return ret_fault;
@@ -548,14 +548,14 @@ AlphaFullCPU<Impl>::AlphaXC::setMiscReg(int misc_reg, const MiscReg &val)
 
 template <class Impl>
 Fault
-AlphaFullCPU<Impl>::AlphaXC::setMiscRegWithEffect(int misc_reg,
+AlphaFullCPU<Impl>::AlphaTC::setMiscRegWithEffect(int misc_reg,
                                                   const MiscReg &val)
 {
     Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, thread->tid);
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
-        cpu->squashFromXC(thread->tid);
+        cpu->squashFromTC(thread->tid);
     }
 
     return ret_fault;
@@ -565,21 +565,21 @@ AlphaFullCPU<Impl>::AlphaXC::setMiscRegWithEffect(int misc_reg,
 
 template <class Impl>
 TheISA::IntReg
-AlphaFullCPU<Impl>::AlphaXC::getSyscallArg(int i)
+AlphaFullCPU<Impl>::AlphaTC::getSyscallArg(int i)
 {
     return cpu->getSyscallArg(i, thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setSyscallArg(int i, IntReg val)
+AlphaFullCPU<Impl>::AlphaTC::setSyscallArg(int i, IntReg val)
 {
     cpu->setSyscallArg(i, val, thread->tid);
 }
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::AlphaXC::setSyscallReturn(SyscallReturn return_value)
+AlphaFullCPU<Impl>::AlphaTC::setSyscallReturn(SyscallReturn return_value)
 {
     cpu->setSyscallReturn(return_value, thread->tid);
 }
@@ -618,10 +618,10 @@ AlphaFullCPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
 
 template <class Impl>
 void
-AlphaFullCPU<Impl>::squashFromXC(unsigned tid)
+AlphaFullCPU<Impl>::squashFromTC(unsigned tid)
 {
     this->thread[tid]->inSyscall = true;
-    this->commit.generateXCEvent(tid);
+    this->commit.generateTCEvent(tid);
 }
 
 #if FULL_SYSTEM
@@ -632,9 +632,9 @@ AlphaFullCPU<Impl>::post_interrupt(int int_num, int index)
 {
     BaseCPU::post_interrupt(int_num, index);
 
-    if (this->thread[0]->status() == ExecContext::Suspended) {
+    if (this->thread[0]->status() == ThreadContext::Suspended) {
         DPRINTF(IPI,"Suspended Processor awoke\n");
-        this->execContexts[0]->activate();
+        this->threadContexts[0]->activate();
     }
 }
 
@@ -673,7 +673,7 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc, unsigned tid)
 {
     if (this->thread[tid]->kernelStats)
         this->thread[tid]->kernelStats->callpal(palFunc,
-                                                this->execContexts[tid]);
+                                                this->threadContexts[tid]);
 
     switch (palFunc) {
       case PAL::halt:
@@ -696,8 +696,8 @@ template <class Impl>
 void
 AlphaFullCPU<Impl>::trap(Fault fault, unsigned tid)
 {
-    // Pass the thread's XC into the invoke method.
-    fault->invoke(this->execContexts[tid]);
+    // Pass the thread's TC into the invoke method.
+    fault->invoke(this->threadContexts[tid]);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/alpha_dyn_inst_impl.hh b/src/cpu/o3/alpha_dyn_inst_impl.hh
index 3a0727b45..a73cf4a7d 100644
--- a/src/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha_dyn_inst_impl.hh
@@ -67,9 +67,9 @@ Fault
 AlphaDynInst<Impl>::execute()
 {
     // @todo: Pretty convoluted way to avoid squashing from happening
-    // when using the XC during an instruction's execution
+    // when using the TC during an instruction's execution
     // (specifically for instructions that have side-effects that use
-    // the XC).  Fix this.
+    // the TC).  Fix this.
     bool in_syscall = this->thread->inSyscall;
     this->thread->inSyscall = true;
 
@@ -85,9 +85,9 @@ Fault
 AlphaDynInst<Impl>::initiateAcc()
 {
     // @todo: Pretty convoluted way to avoid squashing from happening
-    // when using the XC during an instruction's execution
+    // when using the TC during an instruction's execution
     // (specifically for instructions that have side-effects that use
-    // the XC).  Fix this.
+    // the TC).  Fix this.
     bool in_syscall = this->thread->inSyscall;
     this->thread->inSyscall = true;
 
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index eef96b5fd..b7404c488 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -210,9 +210,9 @@ class DefaultCommit
     void generateTrapEvent(unsigned tid);
 
     /** Records that commit needs to initiate a squash due to an
-     * external state update through the XC.
+     * external state update through the TC.
      */
-    void generateXCEvent(unsigned tid);
+    void generateTCEvent(unsigned tid);
 
   private:
     /** Updates the overall status of commit with the nextStatus, and
@@ -242,8 +242,8 @@ class DefaultCommit
     /** Handles squashing due to a trap. */
     void squashFromTrap(unsigned tid);
 
-    /** Handles squashing due to an XC write. */
-    void squashFromXC(unsigned tid);
+    /** Handles squashing due to an TC write. */
+    void squashFromTC(unsigned tid);
 
     /** Commits as many instructions as possible. */
     void commitInsts();
@@ -344,7 +344,7 @@ class DefaultCommit
     bool trapSquash[Impl::MaxThreads];
 
     /** Records if a thread has to squash this cycle due to an XC write. */
-    bool xcSquash[Impl::MaxThreads];
+    bool tcSquash[Impl::MaxThreads];
 
     /** Priority List used for Commit Policy */
     std::list<unsigned> priority_list;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 629acb310..8ee47e907 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -115,7 +115,7 @@ DefaultCommit<Impl>::DefaultCommit(Params *params)
         commitStatus[i] = Idle;
         changedROBNumEntries[i] = false;
         trapSquash[i] = false;
-        xcSquash[i] = false;
+        tcSquash[i] = false;
         PC[i] = nextPC[i] = 0;
     }
 
@@ -384,7 +384,7 @@ DefaultCommit<Impl>::takeOverFrom()
         commitStatus[i] = Idle;
         changedROBNumEntries[i] = false;
         trapSquash[i] = false;
-        xcSquash[i] = false;
+        tcSquash[i] = false;
     }
     squashCounter = 0;
     rob->takeOverFrom();
@@ -482,11 +482,11 @@ DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
 
 template <class Impl>
 void
-DefaultCommit<Impl>::generateXCEvent(unsigned tid)
+DefaultCommit<Impl>::generateTCEvent(unsigned tid)
 {
-    DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
+    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
 
-    xcSquash[tid] = true;
+    tcSquash[tid] = true;
 }
 
 template <class Impl>
@@ -545,11 +545,11 @@ DefaultCommit<Impl>::squashFromTrap(unsigned tid)
 
 template <class Impl>
 void
-DefaultCommit<Impl>::squashFromXC(unsigned tid)
+DefaultCommit<Impl>::squashFromTC(unsigned tid)
 {
     squashAll(tid);
 
-    DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
+    DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
 
     thread[tid]->inSyscall = false;
     assert(!thread[tid]->trapPending);
@@ -557,7 +557,7 @@ DefaultCommit<Impl>::squashFromXC(unsigned tid)
     commitStatus[tid] = ROBSquashing;
     cpu->activityThisCycle();
 
-    xcSquash[tid] = false;
+    tcSquash[tid] = false;
 
     ++squashCounter;
 }
@@ -651,7 +651,7 @@ DefaultCommit<Impl>::commit()
         cpu->check_interrupts() &&
         !cpu->inPalMode(readPC()) &&
         !trapSquash[0] &&
-        !xcSquash[0]) {
+        !tcSquash[0]) {
         // Tell fetch that there is an interrupt pending.  This will
         // make fetch wait until it sees a non PAL-mode PC, at which
         // point it stops fetching instructions.
@@ -720,10 +720,10 @@ DefaultCommit<Impl>::commit()
         // Not sure which one takes priority.  I think if we have
         // both, that's a bad sign.
         if (trapSquash[tid] == true) {
-            assert(!xcSquash[tid]);
+            assert(!tcSquash[tid]);
             squashFromTrap(tid);
-        } else if (xcSquash[tid] == true) {
-            squashFromXC(tid);
+        } else if (tcSquash[tid] == true) {
+            squashFromTC(tid);
         }
 
         // Squashed sequence number must be older than youngest valid
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index ec804ee96..f523766cc 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -39,7 +39,7 @@
 #include "cpu/activity.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/o3/alpha_dyn_inst.hh"
 #include "cpu/o3/alpha_impl.hh"
 #include "cpu/o3/cpu.hh"
@@ -384,7 +384,7 @@ void
 FullO3CPU<Impl>::init()
 {
     if (!deferRegistration) {
-        registerExecContexts();
+        registerThreadContexts();
     }
 
     // Set inSyscall so that the CPU doesn't squash when initially
@@ -394,17 +394,17 @@ FullO3CPU<Impl>::init()
 
     for (int tid=0; tid < number_of_threads; tid++) {
 #if FULL_SYSTEM
-        ExecContext *src_xc = execContexts[tid];
+        ThreadContext *src_tc = threadContexts[tid];
 #else
-        ExecContext *src_xc = thread[tid]->getXCProxy();
+        ThreadContext *src_tc = thread[tid]->getTC();
 #endif
         // Threads start in the Suspended State
-        if (src_xc->status() != ExecContext::Suspended) {
+        if (src_tc->status() != ThreadContext::Suspended) {
             continue;
         }
 
 #if FULL_SYSTEM
-        TheISA::initCPU(src_xc, src_xc->readCpuId());
+        TheISA::initCPU(src_tc, src_tc->readCpuId());
 #endif
     }
 
@@ -430,9 +430,9 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
     // and not in the CPUExecContext.
 #if 0
 #if FULL_SYSTEM
-    ExecContext *src_xc = system->execContexts[tid];
+    ThreadContext *src_tc = system->threadContexts[tid];
 #else
-    CPUExecContext *src_xc = thread[tid];
+    CPUExecContext *src_tc = thread[tid];
 #endif
 
     //Bind Int Regs to Rename Map
@@ -452,13 +452,13 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
     }
 
     //Copy Thread Data Into RegFile
-    this->copyFromXC(tid);
+    this->copyFromTC(tid);
 
     //Set PC/NPC
-    regFile.pc[tid]  = src_xc->readPC();
-    regFile.npc[tid] = src_xc->readNextPC();
+    regFile.pc[tid]  = src_tc->readPC();
+    regFile.npc[tid] = src_tc->readNextPC();
 
-    src_xc->setStatus(ExecContext::Active);
+    src_tc->setStatus(ThreadContext::Active);
 
     activateContext(tid,1);
 
@@ -496,7 +496,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
      * in the sense that it's finished (exiting)? If the thread is just
      * being suspended we might...
      */
-//    this->copyToXC(tid);
+//    this->copyToTC(tid);
 
     //Squash Throughout Pipeline
     fetch.squash(0,tid);
@@ -745,9 +745,9 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
 
     // Set all statuses to active, schedule the CPU's tick event.
     // @todo: Fix up statuses so this is handled properly
-    for (int i = 0; i < execContexts.size(); ++i) {
-        ExecContext *xc = execContexts[i];
-        if (xc->status() == ExecContext::Active && _status != Running) {
+    for (int i = 0; i < threadContexts.size(); ++i) {
+        ThreadContext *tc = threadContexts[i];
+        if (tc->status() == ThreadContext::Active && _status != Running) {
             _status = Running;
             tickEvent.schedule(curTick);
         }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index c2c5289bf..69f52f147 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -52,7 +52,7 @@
 
 template <class>
 class Checker;
-class ExecContext;
+class ThreadContext;
 class MemObject;
 class Process;
 
@@ -455,10 +455,10 @@ class FullO3CPU : public BaseFullCPU
     int getFreeTid();
 
   public:
-    /** Returns a pointer to a thread's exec context. */
-    ExecContext *xcBase(unsigned tid)
+    /** Returns a pointer to a thread context. */
+    ThreadContext *tcBase(unsigned tid)
     {
-        return thread[tid]->getXCProxy();
+        return thread[tid]->getTC();
     }
 
     /** The global sequence number counter. */
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 3a41de721..f3793db6d 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1011,7 +1011,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                     tid, instruction->staticInst->disassemble(fetch_PC));
 
             instruction->traceData =
-                Trace::getInstRecord(curTick, cpu->xcBase(tid), cpu,
+                Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
                                      instruction->staticInst,
                                      instruction->readPC(),tid);
 
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index c2ad75060..ee95b9ab8 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -240,7 +240,7 @@ class PhysRegFile
                                   unsigned thread_id)
     {
         return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
-                                                     cpu->xcBase(thread_id));
+                                                     cpu->tcBase(thread_id));
     }
 
     Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
@@ -252,7 +252,7 @@ class PhysRegFile
                                unsigned thread_id)
     {
         return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
-                                                    cpu->xcBase(thread_id));
+                                                    cpu->tcBase(thread_id));
     }
 
 #if FULL_SYSTEM
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 3fa60f093..7322161e6 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -31,7 +31,7 @@
 
 #include "arch/faults.hh"
 #include "arch/isa_traits.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
 
 class Event;
@@ -49,13 +49,13 @@ class Process;
 /**
  * Class that has various thread state, such as the status, the
  * current instruction being processed, whether or not the thread has
- * a trap pending or is being externally updated, the ExecContext
- * proxy pointer, etc.  It also handles anything related to a specific
+ * a trap pending or is being externally updated, the ThreadContext
+ * pointer, etc.  It also handles anything related to a specific
  * thread's process, such as syscalls and checking valid addresses.
  */
 template <class Impl>
 struct O3ThreadState : public ThreadState {
-    typedef ExecContext::Status Status;
+    typedef ThreadContext::Status Status;
     typedef typename Impl::FullCPU FullCPU;
 
     /** Current status of the thread. */
@@ -93,12 +93,11 @@ struct O3ThreadState : public ThreadState {
     { }
 #endif
 
-    /** Pointer to the ExecContext of this thread.  @todo: Don't call
-     this a proxy.*/
-    ExecContext *xcProxy;
+    /** Pointer to the ThreadContext of this thread. */
+    ThreadContext *tc;
 
-    /** Returns a pointer to the XC of this thread. */
-    ExecContext *getXCProxy() { return xcProxy; }
+    /** Returns a pointer to the TC of this thread. */
+    ThreadContext *getTC() { return tc; }
 
     /** Returns the status of this thread. */
     Status status() const { return _status; }
@@ -121,7 +120,7 @@ struct O3ThreadState : public ThreadState {
 
 #if !FULL_SYSTEM
     /** Handles the syscall. */
-    void syscall(int64_t callnum) { process->syscall(callnum, xcProxy); }
+    void syscall(int64_t callnum) { process->syscall(callnum, tc); }
 #endif
 };
 
diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh
index 63823363e..75ef310b3 100644
--- a/src/cpu/ozone/back_end.hh
+++ b/src/cpu/ozone/back_end.hh
@@ -14,7 +14,7 @@
 #include "mem/request.hh"
 #include "sim/eventq.hh"
 
-class ExecContext;
+class ThreadContext;
 
 template <class Impl>
 class OzoneThreadState;
@@ -172,8 +172,8 @@ class BackEnd
     void setFrontEnd(FrontEnd *front_end_ptr)
     { frontEnd = front_end_ptr; }
 
-    void setXC(ExecContext *xc_ptr)
-    { xc = xc_ptr; }
+    void setTC(ThreadContext *tc_ptr)
+    { tc = tc_ptr; }
 
     void setThreadState(Thread *thread_ptr)
     { thread = thread_ptr; }
@@ -182,8 +182,8 @@ class BackEnd
 
     void tick();
     void squash();
-    void squashFromXC();
-    bool xcSquash;
+    void squashFromTC();
+    bool tcSquash;
 
     template <class T>
     Fault read(RequestPtr req, T &data, int load_idx);
@@ -240,7 +240,7 @@ class BackEnd
 
     FrontEnd *frontEnd;
 
-    ExecContext *xc;
+    ThreadContext *tc;
 
     Thread *thread;
 
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index d82527c8d..55e3813ae 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -37,7 +37,7 @@
 #include "base/timebuf.hh"
 #include "config/full_system.hh"
 #include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/ozone/rename_table.hh"
 #include "cpu/ozone/thread_state.hh"
@@ -101,7 +101,7 @@ class OzoneCPU : public BaseCPU
     typedef TheISA::MiscReg MiscReg;
 
   public:
-    class OzoneXC : public ExecContext {
+    class OzoneTC : public ThreadContext {
       public:
         OzoneCPU<Impl> *cpu;
 
@@ -150,7 +150,7 @@ class OzoneCPU : public BaseCPU
         void dumpFuncProfile();
 #endif
 
-        void takeOverFrom(ExecContext *old_context);
+        void takeOverFrom(ThreadContext *old_context);
 
         void regStats(const std::string &name);
 
@@ -172,7 +172,7 @@ class OzoneCPU : public BaseCPU
         // Also somewhat obnoxious.  Really only used for the TLB fault.
         TheISA::MachInst getInst();
 
-        void copyArchRegs(ExecContext *xc);
+        void copyArchRegs(ThreadContext *tc);
 
         void clearArchRegs();
 
@@ -254,10 +254,13 @@ class OzoneCPU : public BaseCPU
         { panic("Not supported on Alpha!"); }
     };
 
-    // execution context proxy
-    OzoneXC ozoneXC;
-    ExecContext *xcProxy;
-    ExecContext *checkerXC;
+    // Ozone specific thread context
+    OzoneTC ozoneTC;
+    // Thread context to be used
+    ThreadContext *tc;
+    // Checker thread context; will wrap the OzoneTC if a checker is
+    // being used.
+    ThreadContext *checkerTC;
 
     typedef OzoneThreadState<Impl> ImplState;
 
@@ -538,8 +541,8 @@ class OzoneCPU : public BaseCPU
         // and all other stores (WH64?).  Unsuccessful Store
         // Conditionals would have returned above, and wouldn't fall
         // through.
-        for (int i = 0; i < this->system->execContexts.size(); i++){
-            xc = this->system->execContexts[i];
+        for (int i = 0; i < this->system->threadContexts.size(); i++){
+            xc = this->system->threadContexts[i];
             if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
                 (req->paddr & ~0xf)) {
                 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
@@ -595,7 +598,7 @@ class OzoneCPU : public BaseCPU
     InstSeqNum globalSeqNum;
 
   public:
-    void squashFromXC();
+    void squashFromTC();
 
     // @todo: This can be a useful debug function.  Implement it.
     void dumpInsts() { frontEnd->dumpInsts(); }
@@ -613,7 +616,7 @@ class OzoneCPU : public BaseCPU
     void setSyscallReturn(SyscallReturn return_value, int tid);
 #endif
 
-    ExecContext *xcBase() { return xcProxy; }
+    ThreadContext *tcBase() { return tc; }
 
     bool decoupledFrontEnd;
     struct CommStruct {
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index c8803813d..0763a30b3 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -37,7 +37,7 @@
 #include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/ozone/cpu.hh"
 #include "cpu/quiesce_event.hh"
@@ -121,28 +121,28 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 #if FULL_SYSTEM
         checker->setSystem(p->system);
 #endif
-        checkerXC = new CheckerExecContext<OzoneXC>(&ozoneXC, checker);
-        thread.xcProxy = checkerXC;
-        xcProxy = checkerXC;
+        checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
+        thread.tc = checkerTC;
+        tc = checkerXC;
     } else {
         checker = NULL;
-        thread.xcProxy = &ozoneXC;
-        xcProxy = &ozoneXC;
+        thread.tc = &ozoneTC;
+        tc = &ozoneTC;
     }
 
-    ozoneXC.cpu = this;
-    ozoneXC.thread = &thread;
+    ozoneTC.cpu = this;
+    ozoneTC.thread = &thread;
 
     thread.inSyscall = false;
 
-    thread.setStatus(ExecContext::Suspended);
+    thread.setStatus(ThreadContext::Suspended);
 #if FULL_SYSTEM
     /***** All thread state stuff *****/
     thread.cpu = this;
     thread.tid = 0;
     thread.mem = p->mem;
 
-    thread.quiesceEvent = new EndQuiesceEvent(xcProxy);
+    thread.quiesceEvent = new EndQuiesceEvent(tc);
 
     system = p->system;
     itb = p->itb;
@@ -152,10 +152,10 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 
     if (p->profile) {
         thread.profile = new FunctionProfile(p->system->kernelSymtab);
-        // @todo: This might be better as an ExecContext instead of OzoneXC
+        // @todo: This might be better as an ThreadContext instead of OzoneTC
         Callback *cb =
-            new MakeCallback<OzoneXC,
-            &OzoneXC::dumpFuncProfile>(&ozoneXC);
+            new MakeCallback<OzoneTC,
+            &OzoneTC::dumpFuncProfile>(&ozoneTC);
         registerExitCallback(cb);
     }
 
@@ -174,13 +174,13 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     numInst = 0;
     startNumInst = 0;
 
-    execContexts.push_back(xcProxy);
+    threadContexts.push_back(tc);
 
     frontEnd->setCPU(this);
     backEnd->setCPU(this);
 
-    frontEnd->setXC(xcProxy);
-    backEnd->setXC(xcProxy);
+    frontEnd->setTC(tc);
+    backEnd->setTC(tc);
 
     frontEnd->setThreadState(&thread);
     backEnd->setThreadState(&thread);
@@ -263,11 +263,11 @@ OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
         comm.advance();
     }
 
-    // if any of this CPU's ExecContexts are active, mark the CPU as
+    // if any of this CPU's ThreadContexts are active, mark the CPU as
     // running and schedule its tick event.
-    for (int i = 0; i < execContexts.size(); ++i) {
-        ExecContext *xc = execContexts[i];
-        if (xc->status() == ExecContext::Active &&
+    for (int i = 0; i < threadContexts.size(); ++i) {
+        ThreadContext *tc = threadContexts[i];
+        if (tc->status() == ThreadContext::Active &&
             _status != Running) {
             _status = Running;
             tickEvent.schedule(curTick);
@@ -291,7 +291,7 @@ OzoneCPU<Impl>::activateContext(int thread_num, int delay)
     notIdleFraction++;
     scheduleTickEvent(delay);
     _status = Running;
-    thread._status = ExecContext::Active;
+    thread._status = ThreadContext::Active;
     frontEnd->wakeFromQuiesce();
 }
 
@@ -381,11 +381,11 @@ OzoneCPU<Impl>::init()
     // Mark this as in syscall so it won't need to squash
     thread.inSyscall = true;
 #if FULL_SYSTEM
-    for (int i = 0; i < execContexts.size(); ++i) {
-        ExecContext *xc = execContexts[i];
+    for (int i = 0; i < threadContexts.size(); ++i) {
+        ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(xc, xc->readCpuId());
+        TheISA::initCPU(tc, tc->readCpuId());
     }
 #endif
     frontEnd->renameTable.copyFrom(thread.renameTable);
@@ -400,8 +400,8 @@ OzoneCPU<Impl>::serialize(std::ostream &os)
 {
     BaseCPU::serialize(os);
     SERIALIZE_ENUM(_status);
-    nameOut(os, csprintf("%s.xc", name()));
-    ozoneXC.serialize(os);
+    nameOut(os, csprintf("%s.tc", name()));
+    ozoneTC.serialize(os);
     nameOut(os, csprintf("%s.tickEvent", name()));
     tickEvent.serialize(os);
 }
@@ -412,7 +412,7 @@ OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
 {
     BaseCPU::unserialize(cp, section);
     UNSERIALIZE_ENUM(_status);
-    ozoneXC.unserialize(cp, csprintf("%s.xc", section));
+    ozoneTC.unserialize(cp, csprintf("%s.tc", section));
     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 }
 
@@ -440,16 +440,16 @@ OzoneCPU<Impl>::copySrcTranslate(Addr src)
     memReq->reset(src & ~(blk_size - 1), blk_size);
 
     // translate to physical address
-    Fault fault = xc->translateDataReadReq(memReq);
+    Fault fault = tc->translateDataReadReq(memReq);
 
     assert(fault != Alignment_Fault);
 
     if (fault == NoFault) {
-        xc->copySrcAddr = src;
-        xc->copySrcPhysAddr = memReq->paddr + offset;
+        tc->copySrcAddr = src;
+        tc->copySrcPhysAddr = memReq->paddr + offset;
     } else {
-        xc->copySrcAddr = 0;
-        xc->copySrcPhysAddr = 0;
+        tc->copySrcAddr = 0;
+        tc->copySrcPhysAddr = 0;
     }
     return fault;
 #endif
@@ -467,7 +467,7 @@ OzoneCPU<Impl>::copy(Addr dest)
     // Only support block sizes of 64 atm.
     assert(blk_size == 64);
     uint8_t data[blk_size];
-    //assert(xc->copySrcAddr);
+    //assert(tc->copySrcAddr);
     int offset = dest & (blk_size - 1);
 
     // Make sure block doesn't span page
@@ -480,21 +480,21 @@ OzoneCPU<Impl>::copy(Addr dest)
 
     memReq->reset(dest & ~(blk_size -1), blk_size);
     // translate to physical address
-    Fault fault = xc->translateDataWriteReq(memReq);
+    Fault fault = tc->translateDataWriteReq(memReq);
 
     assert(fault != Alignment_Fault);
 
     if (fault == NoFault) {
         Addr dest_addr = memReq->paddr + offset;
         // Need to read straight from memory since we have more than 8 bytes.
-        memReq->paddr = xc->copySrcPhysAddr;
-        xc->mem->read(memReq, data);
+        memReq->paddr = tc->copySrcPhysAddr;
+        tc->mem->read(memReq, data);
         memReq->paddr = dest_addr;
-        xc->mem->write(memReq, data);
+        tc->mem->write(memReq, data);
         if (dcacheInterface) {
             memReq->cmd = Copy;
             memReq->completionEvent = NULL;
-            memReq->paddr = xc->copySrcPhysAddr;
+            memReq->paddr = tc->copySrcPhysAddr;
             memReq->dest = dest_addr;
             memReq->size = 64;
             memReq->time = curTick;
@@ -510,7 +510,7 @@ template <class Impl>
 Addr
 OzoneCPU<Impl>::dbg_vtophys(Addr addr)
 {
-    return vtophys(xcProxy, addr);
+    return vtophys(tcProxy, addr);
 }
 #endif // FULL_SYSTEM
 
@@ -524,7 +524,7 @@ OzoneCPU<Impl>::post_interrupt(int int_num, int index)
     if (_status == Idle) {
         DPRINTF(IPI,"Suspended Processor awoke\n");
 //	thread.activate();
-        // Hack for now.  Otherwise might have to go through the xcProxy, or
+        // Hack for now.  Otherwise might have to go through the tc, or
         // I need to figure out what's the right thing to call.
         activateContext(thread.tid, 1);
     }
@@ -556,10 +556,10 @@ OzoneCPU<Impl>::tick()
 
 template <class Impl>
 void
-OzoneCPU<Impl>::squashFromXC()
+OzoneCPU<Impl>::squashFromTC()
 {
     thread.inSyscall = true;
-    backEnd->generateXCEvent();
+    backEnd->generateTCEvent();
 }
 
 #if !FULL_SYSTEM
@@ -567,7 +567,7 @@ template <class Impl>
 void
 OzoneCPU<Impl>::syscall()
 {
-    // Not sure this copy is needed, depending on how the XC proxy is made.
+    // Not sure this copy is needed, depending on how the TC proxy is made.
     thread.renameTable.copyFrom(backEnd->renameTable);
 
     thread.inSyscall = true;
@@ -576,7 +576,7 @@ OzoneCPU<Impl>::syscall()
 
     DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
 
-    thread.process->syscall(xcProxy);
+    thread.process->syscall(yc);
 
     thread.funcExeInst--;
 
@@ -674,7 +674,7 @@ OzoneCPU<Impl>::processInterrupts()
             checker->cpuXCBase()->setMiscReg(IPR_INTID, ipl);
         }
         Fault fault = new InterruptFault;
-        fault->invoke(thread.getXCProxy());
+        fault->invoke(thread.getTC());
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                 thread.readMiscReg(IPR_IPLR), ipl, summary);
     }
@@ -686,7 +686,7 @@ OzoneCPU<Impl>::simPalCheck(int palFunc)
 {
     // Need to move this to ISA code
     // May also need to make this per thread
-    thread.kernelStats->callpal(palFunc, xcProxy);
+    thread.kernelStats->callpal(palFunc, tc);
 
     switch (palFunc) {
       case PAL::halt:
@@ -708,14 +708,14 @@ OzoneCPU<Impl>::simPalCheck(int palFunc)
 
 template <class Impl>
 BaseCPU *
-OzoneCPU<Impl>::OzoneXC::getCpuPtr()
+OzoneCPU<Impl>::OzoneTC::getCpuPtr()
 {
     return cpu;
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::setCpuId(int id)
+OzoneCPU<Impl>::OzoneTC::setCpuId(int id)
 {
     cpu->cpuId = id;
     thread->cpuId = id;
@@ -723,14 +723,14 @@ OzoneCPU<Impl>::OzoneXC::setCpuId(int id)
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::setStatus(Status new_status)
+OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
 {
     thread->_status = new_status;
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::activate(int delay)
+OzoneCPU<Impl>::OzoneTC::activate(int delay)
 {
     cpu->activateContext(thread->tid, delay);
 }
@@ -738,7 +738,7 @@ OzoneCPU<Impl>::OzoneXC::activate(int delay)
 /// Set the status to Suspended.
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::suspend()
+OzoneCPU<Impl>::OzoneTC::suspend()
 {
     cpu->suspendContext(thread->tid);
 }
@@ -746,7 +746,7 @@ OzoneCPU<Impl>::OzoneXC::suspend()
 /// Set the status to Unallocated.
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::deallocate()
+OzoneCPU<Impl>::OzoneTC::deallocate()
 {
     cpu->deallocateContext(thread->tid);
 }
@@ -754,7 +754,7 @@ OzoneCPU<Impl>::OzoneXC::deallocate()
 /// Set the status to Halted.
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::halt()
+OzoneCPU<Impl>::OzoneTC::halt()
 {
     cpu->haltContext(thread->tid);
 }
@@ -762,13 +762,13 @@ OzoneCPU<Impl>::OzoneXC::halt()
 #if FULL_SYSTEM
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::dumpFuncProfile()
+OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
 { }
 #endif
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context)
+OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
     assert(getMemPtr() == old_context->getMemPtr());
@@ -788,12 +788,12 @@ OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context)
 #else
     EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
     if (other_quiesce) {
-        // Point the quiesce event's XC at this XC so that it wakes up
+        // Point the quiesce event's TC at this TC so that it wakes up
         // the proper CPU.
-        other_quiesce->xc = this;
+        other_quiesce->tc = this;
     }
     if (thread->quiesceEvent) {
-        thread->quiesceEvent->xc = this;
+        thread->quiesceEvent->tc = this;
     }
 
     thread->kernelStats = old_context->getKernelStats();
@@ -801,12 +801,12 @@ OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context)
     cpu->lockFlag = false;
 #endif
 
-    old_context->setStatus(ExecContext::Unallocated);
+    old_context->setStatus(ThreadContext::Unallocated);
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::regStats(const std::string &name)
+OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
 {
 #if FULL_SYSTEM
     thread->kernelStats = new Kernel::Statistics(cpu->system);
@@ -816,39 +816,39 @@ OzoneCPU<Impl>::OzoneXC::regStats(const std::string &name)
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::serialize(std::ostream &os)
+OzoneCPU<Impl>::OzoneTC::serialize(std::ostream &os)
 { }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::unserialize(Checkpoint *cp, const std::string &section)
+OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string &section)
 { }
 
 #if FULL_SYSTEM
 template <class Impl>
 EndQuiesceEvent *
-OzoneCPU<Impl>::OzoneXC::getQuiesceEvent()
+OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
 {
     return thread->quiesceEvent;
 }
 
 template <class Impl>
 Tick
-OzoneCPU<Impl>::OzoneXC::readLastActivate()
+OzoneCPU<Impl>::OzoneTC::readLastActivate()
 {
     return thread->lastActivate;
 }
 
 template <class Impl>
 Tick
-OzoneCPU<Impl>::OzoneXC::readLastSuspend()
+OzoneCPU<Impl>::OzoneTC::readLastSuspend()
 {
     return thread->lastSuspend;
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::profileClear()
+OzoneCPU<Impl>::OzoneTC::profileClear()
 {
     if (thread->profile)
         thread->profile->clear();
@@ -856,7 +856,7 @@ OzoneCPU<Impl>::OzoneXC::profileClear()
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::profileSample()
+OzoneCPU<Impl>::OzoneTC::profileSample()
 {
     if (thread->profile)
         thread->profile->sample(thread->profileNode, thread->profilePC);
@@ -865,7 +865,7 @@ OzoneCPU<Impl>::OzoneXC::profileSample()
 
 template <class Impl>
 int
-OzoneCPU<Impl>::OzoneXC::getThreadNum()
+OzoneCPU<Impl>::OzoneTC::getThreadNum()
 {
     return thread->tid;
 }
@@ -873,57 +873,57 @@ OzoneCPU<Impl>::OzoneXC::getThreadNum()
 // Also somewhat obnoxious.  Really only used for the TLB fault.
 template <class Impl>
 TheISA::MachInst
-OzoneCPU<Impl>::OzoneXC::getInst()
+OzoneCPU<Impl>::OzoneTC::getInst()
 {
     return thread->inst;
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::copyArchRegs(ExecContext *xc)
+OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
 {
-    thread->PC = xc->readPC();
-    thread->nextPC = xc->readNextPC();
+    thread->PC = tc->readPC();
+    thread->nextPC = tc->readNextPC();
 
     cpu->frontEnd->setPC(thread->PC);
     cpu->frontEnd->setNextPC(thread->nextPC);
 
     for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
         if (i < TheISA::FP_Base_DepTag) {
-            thread->renameTable[i]->setIntResult(xc->readIntReg(i));
+            thread->renameTable[i]->setIntResult(tc->readIntReg(i));
         } else if (i < (TheISA::FP_Base_DepTag + TheISA::NumFloatRegs)) {
             int fp_idx = i - TheISA::FP_Base_DepTag;
             thread->renameTable[i]->setDoubleResult(
-                xc->readFloatRegDouble(fp_idx));
+                tc->readFloatRegDouble(fp_idx));
         }
     }
 
 #if !FULL_SYSTEM
-    thread->funcExeInst = xc->readFuncExeInst();
+    thread->funcExeInst = tc->readFuncExeInst();
 #endif
 
-    // Need to copy the XC values into the current rename table,
+    // Need to copy the TC values into the current rename table,
     // copy the misc regs.
-    thread->regs.miscRegs.copyMiscRegs(xc);
+    thread->regs.miscRegs.copyMiscRegs(tc);
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::clearArchRegs()
+OzoneCPU<Impl>::OzoneTC::clearArchRegs()
 {
     panic("Unimplemented!");
 }
 
 template <class Impl>
 uint64_t
-OzoneCPU<Impl>::OzoneXC::readIntReg(int reg_idx)
+OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
 {
     return thread->renameTable[reg_idx]->readIntResult();
 }
 
 template <class Impl>
 float
-OzoneCPU<Impl>::OzoneXC::readFloatReg(int reg_idx, int width)
+OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
 {
     int idx = reg_idx + TheISA::FP_Base_DepTag;
     switch(width) {
@@ -939,7 +939,7 @@ OzoneCPU<Impl>::OzoneXC::readFloatReg(int reg_idx, int width)
 
 template <class Impl>
 double
-OzoneCPU<Impl>::OzoneXC::readFloatReg(int reg_idx)
+OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
 {
     int idx = reg_idx + TheISA::FP_Base_DepTag;
     return thread->renameTable[idx]->readFloatResult();
@@ -947,7 +947,7 @@ OzoneCPU<Impl>::OzoneXC::readFloatReg(int reg_idx)
 
 template <class Impl>
 uint64_t
-OzoneCPU<Impl>::OzoneXC::readFloatRegBits(int reg_idx, int width)
+OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
 {
     int idx = reg_idx + TheISA::FP_Base_DepTag;
     return thread->renameTable[idx]->readIntResult();
@@ -955,7 +955,7 @@ OzoneCPU<Impl>::OzoneXC::readFloatRegBits(int reg_idx, int width)
 
 template <class Impl>
 uint64_t
-OzoneCPU<Impl>::OzoneXC::readFloatRegBits(int reg_idx)
+OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
 {
     int idx = reg_idx + TheISA::FP_Base_DepTag;
     return thread->renameTable[idx]->readIntResult();
@@ -963,18 +963,18 @@ OzoneCPU<Impl>::OzoneXC::readFloatRegBits(int reg_idx)
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::setIntReg(int reg_idx, uint64_t val)
+OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
 {
     thread->renameTable[reg_idx]->setIntResult(val);
 
     if (!thread->inSyscall) {
-        cpu->squashFromXC();
+        cpu->squashFromTC();
     }
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::setFloatReg(int reg_idx, FloatReg val, int width)
+OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
 {
     int idx = reg_idx + TheISA::FP_Base_DepTag;
     switch(width) {
@@ -989,26 +989,26 @@ OzoneCPU<Impl>::OzoneXC::setFloatReg(int reg_idx, FloatReg val, int width)
     }
 
     if (!thread->inSyscall) {
-        cpu->squashFromXC();
+        cpu->squashFromTC();
     }
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::setFloatReg(int reg_idx, FloatReg val)
+OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
 {
     int idx = reg_idx + TheISA::FP_Base_DepTag;
 
     thread->renameTable[idx]->setDoubleResult(val);
 
     if (!thread->inSyscall) {
-        cpu->squashFromXC();
+        cpu->squashFromTC();
     }
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val,
+OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
                                          int width)
 {
     panic("Unimplemented!");
@@ -1016,45 +1016,45 @@ OzoneCPU<Impl>::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val,
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val)
+OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     panic("Unimplemented!");
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::setPC(Addr val)
+OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
 {
     thread->PC = val;
     cpu->frontEnd->setPC(val);
 
     if (!thread->inSyscall) {
-        cpu->squashFromXC();
+        cpu->squashFromTC();
     }
 }
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneXC::setNextPC(Addr val)
+OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
 {
     thread->nextPC = val;
     cpu->frontEnd->setNextPC(val);
 
     if (!thread->inSyscall) {
-        cpu->squashFromXC();
+        cpu->squashFromTC();
     }
 }
 
 template <class Impl>
 TheISA::MiscReg
-OzoneCPU<Impl>::OzoneXC::readMiscReg(int misc_reg)
+OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
 {
     return thread->regs.miscRegs.readReg(misc_reg);
 }
 
 template <class Impl>
 TheISA::MiscReg
-OzoneCPU<Impl>::OzoneXC::readMiscRegWithEffect(int misc_reg, Fault &fault)
+OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg, Fault &fault)
 {
     return thread->regs.miscRegs.readRegWithEffect(misc_reg,
                                                    fault, this);
@@ -1062,13 +1062,13 @@ OzoneCPU<Impl>::OzoneXC::readMiscRegWithEffect(int misc_reg, Fault &fault)
 
 template <class Impl>
 Fault
-OzoneCPU<Impl>::OzoneXC::setMiscReg(int misc_reg, const MiscReg &val)
+OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
 {
     // Needs to setup a squash event unless we're in syscall mode
     Fault ret_fault = thread->regs.miscRegs.setReg(misc_reg, val);
 
     if (!thread->inSyscall) {
-        cpu->squashFromXC();
+        cpu->squashFromTC();
     }
 
     return ret_fault;
@@ -1076,14 +1076,14 @@ OzoneCPU<Impl>::OzoneXC::setMiscReg(int misc_reg, const MiscReg &val)
 
 template <class Impl>
 Fault
-OzoneCPU<Impl>::OzoneXC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 {
     // Needs to setup a squash event unless we're in syscall mode
     Fault ret_fault = thread->regs.miscRegs.setRegWithEffect(misc_reg, val,
                                                              this);
 
     if (!thread->inSyscall) {
-        cpu->squashFromXC();
+        cpu->squashFromTC();
     }
 
     return ret_fault;
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index b3131149d..45ef6eb4b 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -38,7 +38,7 @@
 #include "sim/eventq.hh"
 #include "sim/stats.hh"
 
-class ExecContext;
+class ThreadContext;
 class MemInterface;
 template <class>
 class OzoneThreadState;
@@ -56,7 +56,7 @@ class FrontEnd
     typedef typename Impl::FullCPU FullCPU;
     typedef typename Impl::BackEnd BackEnd;
 
-    typedef typename Impl::FullCPU::OzoneXC OzoneXC;
+    typedef typename Impl::FullCPU::OzoneTC OzoneTC;
     typedef typename Impl::FullCPU::CommStruct CommStruct;
 
     FrontEnd(Params *params);
@@ -71,7 +71,7 @@ class FrontEnd
 
     void setCommBuffer(TimeBuffer<CommStruct> *_comm);
 
-    void setXC(ExecContext *xc_ptr);
+    void setTC(ThreadContext *tc_ptr);
 
     void setThreadState(OzoneThreadState<Impl> *thread_ptr)
     { thread = thread_ptr; }
@@ -95,7 +95,7 @@ class FrontEnd
 
     void doSwitchOut();
 
-    void takeOverFrom(ExecContext *old_xc = NULL);
+    void takeOverFrom(ThreadContext *old_tc = NULL);
 
     bool isSwitchedOut() { return switchedOut; }
 
@@ -132,7 +132,7 @@ class FrontEnd
 
     BackEnd *backEnd;
 
-    ExecContext *xc;
+    ThreadContext *tc;
 
     OzoneThreadState<Impl> *thread;
 
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index ffbcf3340..bf6a8c144 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -29,7 +29,7 @@
 #include "arch/faults.hh"
 #include "arch/isa_traits.hh"
 #include "base/statistics.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/ozone/front_end.hh"
 #include "mem/mem_interface.hh"
@@ -93,9 +93,9 @@ FrontEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
 
 template <class Impl>
 void
-FrontEnd<Impl>::setXC(ExecContext *xc_ptr)
+FrontEnd<Impl>::setTC(ThreadContext *tc_ptr)
 {
-    xc = xc_ptr;
+    tc = tc_ptr;
 }
 
 template <class Impl>
@@ -407,7 +407,7 @@ FrontEnd<Impl>::fetchCacheLine()
     memReq->asid = 0;
     memReq->thread_num = 0;
     memReq->data = new uint8_t[64];
-    memReq->xc = xc;
+    memReq->tc = tc;
     memReq->cmd = Read;
     memReq->reset(fetch_PC, cacheBlkSize, flags);
 
@@ -780,7 +780,7 @@ FrontEnd<Impl>::getInstFromCacheline()
             instruction->staticInst->disassemble(PC));
 
     instruction->traceData =
-        Trace::getInstRecord(curTick, xc, cpu,
+        Trace::getInstRecord(curTick, tc, cpu,
                              instruction->staticInst,
                              instruction->readPC(), 0);
 
@@ -862,7 +862,7 @@ FrontEnd<Impl>::doSwitchOut()
 
 template <class Impl>
 void
-FrontEnd<Impl>::takeOverFrom(ExecContext *old_xc)
+FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
 {
     assert(freeRegs == numPhysRegs);
     fetchCacheLineNextCycle = true;
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index 578ae4ce2..aae2b1c32 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -6,7 +6,7 @@
 
 #include "arch/faults.hh"
 #include "base/timebuf.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/ozone/rename_table.hh"
 #include "cpu/ozone/thread_state.hh"
@@ -22,7 +22,7 @@ class InorderBackEnd
     typedef typename Impl::FullCPU FullCPU;
     typedef typename Impl::FrontEnd FrontEnd;
 
-    typedef typename FullCPU::OzoneXC OzoneXC;
+    typedef typename FullCPU::OzoneTC OzoneTC;
     typedef typename Impl::FullCPU::CommStruct CommStruct;
 
     InorderBackEnd(Params *params);
@@ -38,7 +38,7 @@ class InorderBackEnd
     void setCommBuffer(TimeBuffer<CommStruct> *_comm)
     { comm = _comm; }
 
-    void setXC(ExecContext *xc_ptr);
+    void setTC(ThreadContext *tc_ptr);
 
     void setThreadState(OzoneThreadState<Impl> *thread_ptr);
 
@@ -69,7 +69,7 @@ class InorderBackEnd
   private:
     void handleFault();
 
-    void setSquashInfoFromXC();
+    void setSquashInfoFromTC();
 
     bool squashPending;
     InstSeqNum squashSeqNum;
@@ -98,14 +98,14 @@ class InorderBackEnd
 
     void switchOut() { panic("Not implemented!"); }
     void doSwitchOut() { panic("Not implemented!"); }
-    void takeOverFrom(ExecContext *old_xc = NULL) { panic("Not implemented!"); }
+    void takeOverFrom(ThreadContext *old_tc = NULL) { panic("Not implemented!"); }
 
   public:
     FullCPU *cpu;
 
     FrontEnd *frontEnd;
 
-    ExecContext *xc;
+    ThreadContext *tc;
 
     OzoneThreadState<Impl> *thread;
 
diff --git a/src/cpu/ozone/lw_back_end.hh b/src/cpu/ozone/lw_back_end.hh
index 021381dd0..f0946b8d4 100644
--- a/src/cpu/ozone/lw_back_end.hh
+++ b/src/cpu/ozone/lw_back_end.hh
@@ -44,7 +44,7 @@
 
 template <class>
 class Checker;
-class ExecContext;
+class ThreadContext;
 
 template <class Impl>
 class OzoneThreadState;
@@ -126,8 +126,8 @@ class LWBackEnd
     void setFrontEnd(FrontEnd *front_end_ptr)
     { frontEnd = front_end_ptr; }
 
-    void setXC(ExecContext *xc_ptr)
-    { xc = xc_ptr; }
+    void setTC(ThreadContext *tc_ptr)
+    { tc = tc_ptr; }
 
     void setThreadState(Thread *thread_ptr)
     { thread = thread_ptr; }
@@ -136,12 +136,12 @@ class LWBackEnd
 
     void tick();
     void squash();
-    void generateXCEvent() { xcSquash = true; }
-    void squashFromXC();
+    void generateTCEvent() { tcSquash = true; }
+    void squashFromTC();
     void squashFromTrap();
     void checkInterrupts();
     bool trapSquash;
-    bool xcSquash;
+    bool tcSquash;
 
     template <class T>
     Fault read(RequestPtr req, T &data, int load_idx);
@@ -213,7 +213,7 @@ class LWBackEnd
 
     void switchOut();
     void doSwitchOut();
-    void takeOverFrom(ExecContext *old_xc = NULL);
+    void takeOverFrom(ThreadContext *old_tc = NULL);
 
     bool isSwitchedOut() { return switchedOut; }
 
@@ -241,7 +241,7 @@ class LWBackEnd
 
     FrontEnd *frontEnd;
 
-    ExecContext *xc;
+    ThreadContext *tc;
 
     Thread *thread;
 
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index 41b4ea24b..0f5c01c0d 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -209,7 +209,7 @@ LWBackEnd<Impl>::DCacheCompletionEvent::description()
 template <class Impl>
 LWBackEnd<Impl>::LWBackEnd(Params *params)
     : d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5),
-      trapSquash(false), xcSquash(false), cacheCompletionEvent(this),
+      trapSquash(false), tcSquash(false), cacheCompletionEvent(this),
       dcacheInterface(params->dcacheInterface), width(params->backEndWidth),
       exactFullStall(true)
 {
@@ -592,7 +592,7 @@ LWBackEnd<Impl>::checkInterrupts()
         cpu->check_interrupts() &&
         !cpu->inPalMode(thread->readPC()) &&
         !trapSquash &&
-        !xcSquash) {
+        !tcSquash) {
         frontEnd->interruptPending = true;
         if (robEmpty() && !LSQ.hasStoresToWB()) {
             // Will need to squash all instructions currently in flight and have
@@ -637,7 +637,7 @@ LWBackEnd<Impl>::handleFault(Fault &fault, Tick latency)
 
     // Consider holding onto the trap and waiting until the trap event
     // happens for this to be executed.
-    fault->invoke(thread->getXCProxy());
+    fault->invoke(thread->getTCProxy());
 
     // Exit state update mode to avoid accidental updating.
     thread->inSyscall = false;
@@ -671,10 +671,10 @@ LWBackEnd<Impl>::tick()
     checkInterrupts();
 
     if (trapSquash) {
-        assert(!xcSquash);
+        assert(!tcSquash);
         squashFromTrap();
-    } else if (xcSquash) {
-        squashFromXC();
+    } else if (tcSquash) {
+        squashFromTC();
     }
 #endif
 
@@ -1257,12 +1257,12 @@ LWBackEnd<Impl>::commitInst(int inst_num)
             assert(!thread->inSyscall && !thread->trapPending);
         oldpc = thread->readPC();
         cpu->system->pcEventQueue.service(
-            thread->getXCProxy());
+            thread->getTCProxy());
         count++;
     } while (oldpc != thread->readPC());
     if (count > 1) {
         DPRINTF(BE, "PC skip function event, stopping commit\n");
-        xcSquash = true;
+        tcSquash = true;
         return false;
     }
 #endif
@@ -1396,7 +1396,7 @@ LWBackEnd<Impl>::squash(const InstSeqNum &sn)
 
 template <class Impl>
 void
-LWBackEnd<Impl>::squashFromXC()
+LWBackEnd<Impl>::squashFromTC()
 {
     InstSeqNum squashed_inst = robEmpty() ? 0 : instList.back()->seqNum - 1;
     squash(squashed_inst);
@@ -1406,7 +1406,7 @@ LWBackEnd<Impl>::squashFromXC()
 
     thread->trapPending = false;
     thread->inSyscall = false;
-    xcSquash = false;
+    tcSquash = false;
     commitStatus = Running;
 }
 
@@ -1483,7 +1483,7 @@ LWBackEnd<Impl>::doSwitchOut()
     switchedOut = true;
     switchPending = false;
     // Need to get rid of all committed, non-speculative state and write it
-    // to memory/XC.  In this case this is stores that have committed and not
+    // to memory/TC.  In this case this is stores that have committed and not
     // yet written back.
     assert(robEmpty());
     assert(!LSQ.hasStoresToWB());
@@ -1495,7 +1495,7 @@ LWBackEnd<Impl>::doSwitchOut()
 
 template <class Impl>
 void
-LWBackEnd<Impl>::takeOverFrom(ExecContext *old_xc)
+LWBackEnd<Impl>::takeOverFrom(ThreadContext *old_xc)
 {
     switchedOut = false;
     xcSquash = false;
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index e1488dd6f..d27fa565c 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -234,7 +234,7 @@ class OzoneLWLSQ {
 
     void switchOut();
 
-    void takeOverFrom(ExecContext *old_xc = NULL);
+    void takeOverFrom(ThreadContext *old_tc = NULL);
 
     bool isSwitchedOut() { return switchedOut; }
 
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index f72bbb1cc..0841e0b57 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -846,7 +846,7 @@ OzoneLWLSQ<Impl>::switchOut()
 
 template <class Impl>
 void
-OzoneLWLSQ<Impl>::takeOverFrom(ExecContext *old_xc)
+OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
 {
     // Clear out any old state. May be redundant if this is the first time
     // the CPU is being used.
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index 9b5433815..c91297e73 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -31,7 +31,7 @@
 
 #include "arch/faults.hh"
 #include "arch/isa_traits.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
 #include "sim/process.hh"
 
@@ -52,10 +52,10 @@ class FunctionalMemory;
 // has benefits for SMT; basically serves same use as CPUExecContext.
 // Makes the ExecContext proxy easier.  Gives organization/central access point
 // to state of a thread that can be accessed normally (i.e. not in-flight
-// stuff within a OoO processor).  Does this need an XC proxy within it?
+// stuff within a OoO processor).  Does this need an TC proxy within it?
 template <class Impl>
 struct OzoneThreadState : public ThreadState {
-    typedef typename ExecContext::Status Status;
+    typedef typename ThreadContext::Status Status;
     typedef typename Impl::FullCPU FullCPU;
     typedef TheISA::MiscReg MiscReg;
 
@@ -104,9 +104,9 @@ struct OzoneThreadState : public ThreadState {
 
     bool trapPending;
 
-    ExecContext *xcProxy;
+    ThreadContext *tc;
 
-    ExecContext *getXCProxy() { return xcProxy; }
+    ThreadContext *getTC() { return tc; }
 
 #if !FULL_SYSTEM
     Fault translateInstReq(Request *req)
@@ -145,7 +145,7 @@ struct OzoneThreadState : public ThreadState {
 
     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
     {
-        return regs.readMiscRegWithEffect(misc_reg, fault, xcProxy);
+        return regs.readMiscRegWithEffect(misc_reg, fault, tc);
     }
 
     Fault setMiscReg(int misc_reg, const MiscReg &val)
@@ -155,7 +155,7 @@ struct OzoneThreadState : public ThreadState {
 
     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
-        return regs.setMiscRegWithEffect(misc_reg, val, xcProxy);
+        return regs.setMiscRegWithEffect(misc_reg, val, tc);
     }
 
     uint64_t readPC()
diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index ad94a8457..fca357fe3 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -37,7 +37,7 @@
 #include "base/trace.hh"
 #include "config/full_system.hh"
 #include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/pc_event.hh"
 #include "sim/debug.hh"
 #include "sim/root.hh"
@@ -81,9 +81,9 @@ PCEventQueue::schedule(PCEvent *event)
 }
 
 bool
-PCEventQueue::doService(ExecContext *xc)
+PCEventQueue::doService(ThreadContext *tc)
 {
-    Addr pc = xc->readPC() & ~0x3;
+    Addr pc = tc->readPC() & ~0x3;
     int serviced = 0;
     range_t range = equal_range(pc);
     for (iterator i = range.first; i != range.second; ++i) {
@@ -91,13 +91,13 @@ PCEventQueue::doService(ExecContext *xc)
         // another event.  This for example, prevents two invocations
         // of the SkipFuncEvent.  Maybe we should have separate PC
         // event queues for each processor?
-        if (pc != (xc->readPC() & ~0x3))
+        if (pc != (tc->readPC() & ~0x3))
             continue;
 
         DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n",
                 (*i)->pc(), (*i)->descr());
 
-        (*i)->process(xc);
+        (*i)->process(tc);
         ++serviced;
     }
 
@@ -128,9 +128,9 @@ BreakPCEvent::BreakPCEvent(PCEventQueue *q, const std::string &desc, Addr addr,
 }
 
 void
-BreakPCEvent::process(ExecContext *xc)
+BreakPCEvent::process(ThreadContext *tc)
 {
-    StringWrap name(xc->getCpuPtr()->name() + ".break_event");
+    StringWrap name(tc->getCpuPtr()->name() + ".break_event");
     DPRINTFN("break event %s triggered\n", descr());
     debug_break();
     if (remove)
diff --git a/src/cpu/pc_event.hh b/src/cpu/pc_event.hh
index 819472391..6b048b2c2 100644
--- a/src/cpu/pc_event.hh
+++ b/src/cpu/pc_event.hh
@@ -36,7 +36,7 @@
 
 #include "base/misc.hh"
 
-class ExecContext;
+class ThreadContext;
 class PCEventQueue;
 
 class PCEvent
@@ -58,7 +58,7 @@ class PCEvent
     Addr pc() const { return evpc; }
 
     bool remove();
-    virtual void process(ExecContext *xc) = 0;
+    virtual void process(ThreadContext *tc) = 0;
 };
 
 class PCEventQueue
@@ -90,7 +90,7 @@ class PCEventQueue
   protected:
     map_t pc_map;
 
-    bool doService(ExecContext *xc);
+    bool doService(ThreadContext *tc);
 
   public:
     PCEventQueue();
@@ -98,12 +98,12 @@ class PCEventQueue
 
     bool remove(PCEvent *event);
     bool schedule(PCEvent *event);
-    bool service(ExecContext *xc)
+    bool service(ThreadContext *tc)
     {
         if (pc_map.empty())
             return false;
 
-        return doService(xc);
+        return doService(tc);
     }
 
     range_t equal_range(Addr pc);
@@ -137,7 +137,7 @@ class BreakPCEvent : public PCEvent
   public:
     BreakPCEvent(PCEventQueue *q, const std::string &desc, Addr addr,
                  bool del = false);
-    virtual void process(ExecContext *xc);
+    virtual void process(ThreadContext *tc);
 };
 
 #endif // __PC_EVENT_HH__
diff --git a/src/cpu/profile.cc b/src/cpu/profile.cc
index 5f6ca53c3..4f04615e9 100644
--- a/src/cpu/profile.cc
+++ b/src/cpu/profile.cc
@@ -36,7 +36,7 @@
 #include "base/trace.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/profile.hh"
 
 using namespace std;
@@ -120,7 +120,7 @@ FunctionProfile::clear()
 }
 
 void
-FunctionProfile::dump(ExecContext *xc, ostream &os) const
+FunctionProfile::dump(ThreadContext *tc, ostream &os) const
 {
     ccprintf(os, ">>>PC data\n");
     map<Addr, Counter>::const_iterator i, end = pc_count.end();
diff --git a/src/cpu/profile.hh b/src/cpu/profile.hh
index 8f5be4001..7f9625241 100644
--- a/src/cpu/profile.hh
+++ b/src/cpu/profile.hh
@@ -37,7 +37,7 @@
 #include "sim/host.hh"
 #include "arch/stacktrace.hh"
 
-class ExecContext;
+class ThreadContext;
 
 class ProfileNode
 {
@@ -72,17 +72,17 @@ class FunctionProfile
     FunctionProfile(const SymbolTable *symtab);
     ~FunctionProfile();
 
-    ProfileNode *consume(ExecContext *xc, StaticInstPtr inst);
+    ProfileNode *consume(ThreadContext *tc, StaticInstPtr inst);
     ProfileNode *consume(const std::vector<Addr> &stack);
     void clear();
-    void dump(ExecContext *xc, std::ostream &out) const;
+    void dump(ThreadContext *tc, std::ostream &out) const;
     void sample(ProfileNode *node, Addr pc);
 };
 
 inline ProfileNode *
-FunctionProfile::consume(ExecContext *xc, StaticInstPtr inst)
+FunctionProfile::consume(ThreadContext *tc, StaticInstPtr inst)
 {
-    if (!trace.trace(xc, inst))
+    if (!trace.trace(tc, inst))
         return NULL;
     trace.dprintf();
     return consume(trace.getstack());
diff --git a/src/cpu/quiesce_event.cc b/src/cpu/quiesce_event.cc
index 37814ae09..664a7aa01 100644
--- a/src/cpu/quiesce_event.cc
+++ b/src/cpu/quiesce_event.cc
@@ -1,16 +1,16 @@
 
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/quiesce_event.hh"
 
-EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc)
-    : Event(&mainEventQueue), xc(_xc)
+EndQuiesceEvent::EndQuiesceEvent(ThreadContext *_tc)
+    : Event(&mainEventQueue), tc(_tc)
 {
 }
 
 void
 EndQuiesceEvent::process()
 {
-    xc->activate();
+    tc->activate();
 }
 
 const char*
diff --git a/src/cpu/quiesce_event.hh b/src/cpu/quiesce_event.hh
index 18e88ecce..cc6adf828 100644
--- a/src/cpu/quiesce_event.hh
+++ b/src/cpu/quiesce_event.hh
@@ -3,15 +3,15 @@
 
 #include "sim/eventq.hh"
 
-class ExecContext;
+class ThreadContext;
 
 /** Event for timing out quiesce instruction */
 struct EndQuiesceEvent : public Event
 {
-    /** A pointer to the execution context that is quiesced */
-    ExecContext *xc;
+    /** A pointer to the thread context that is quiesced */
+    ThreadContext *tc;
 
-    EndQuiesceEvent(ExecContext *_xc);
+    EndQuiesceEvent(ThreadContext *_tc);
 
     /** Event process to occur at interrupt*/
     virtual void process();
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 2d47f9624..91ac0b6a5 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -70,11 +70,11 @@ AtomicSimpleCPU::init()
 
     BaseCPU::init();
 #if FULL_SYSTEM
-    for (int i = 0; i < execContexts.size(); ++i) {
-        ExecContext *xc = execContexts[i];
+    for (int i = 0; i < threadContexts.size(); ++i) {
+        ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(xc, xc->readCpuId());
+        TheISA::initCPU(tc, tc->readCpuId());
     }
 #endif
 }
@@ -179,11 +179,11 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 
     assert(!tickEvent.scheduled());
 
-    // if any of this CPU's ExecContexts are active, mark the CPU as
+    // if any of this CPU's ThreadContexts are active, mark the CPU as
     // running and schedule its tick event.
-    for (int i = 0; i < execContexts.size(); ++i) {
-        ExecContext *xc = execContexts[i];
-        if (xc->status() == ExecContext::Active && _status != Running) {
+    for (int i = 0; i < threadContexts.size(); ++i) {
+        ThreadContext *tc = threadContexts[i];
+        if (tc->status() == ThreadContext::Active && _status != Running) {
             _status = Running;
             tickEvent.schedule(curTick);
             break;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 12fb4f165..d36aa93a2 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -39,7 +39,7 @@
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/profile.hh"
 #include "cpu/sampler/sampler.hh"
@@ -79,9 +79,9 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p)
             /* asid */ 0, mem);
 #endif // !FULL_SYSTEM
 
-    cpuXC->setStatus(ExecContext::Suspended);
+    cpuXC->setStatus(ThreadContext::Suspended);
 
-    xcProxy = cpuXC->getProxy();
+    tc = cpuXC->getTC();
 
     numInst = 0;
     startNumInst = 0;
@@ -90,7 +90,7 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p)
     lastIcacheStall = 0;
     lastDcacheStall = 0;
 
-    execContexts.push_back(xcProxy);
+    threadContexts.push_back(tc);
 }
 
 BaseSimpleCPU::~BaseSimpleCPU()
@@ -290,7 +290,7 @@ BaseSimpleCPU::copy(Addr dest)
 Addr
 BaseSimpleCPU::dbg_vtophys(Addr addr)
 {
-    return vtophys(xcProxy, addr);
+    return vtophys(tc, addr);
 }
 #endif // FULL_SYSTEM
 
@@ -300,7 +300,7 @@ BaseSimpleCPU::post_interrupt(int int_num, int index)
 {
     BaseCPU::post_interrupt(int_num, index);
 
-    if (cpuXC->status() == ExecContext::Suspended) {
+    if (cpuXC->status() == ThreadContext::Suspended) {
                 DPRINTF(IPI,"Suspended Processor awoke\n");
         cpuXC->activate();
     }
@@ -344,7 +344,7 @@ BaseSimpleCPU::checkForInterrupts()
             cpuXC->setMiscReg(IPR_ISR, summary);
             cpuXC->setMiscReg(IPR_INTID, ipl);
 
-            Fault(new InterruptFault)->invoke(xcProxy);
+            Fault(new InterruptFault)->invoke(tc);
 
             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                     cpuXC->readMiscReg(IPR_IPLR), ipl, summary);
@@ -393,7 +393,7 @@ BaseSimpleCPU::preExecute()
     inst = gtoh(inst);
     curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC()));
 
-    traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
+    traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst,
                                      cpuXC->readPC());
 
     DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
@@ -411,14 +411,14 @@ BaseSimpleCPU::postExecute()
 #if FULL_SYSTEM
     if (system->kernelBinning->fnbin) {
         assert(cpuXC->getKernelStats());
-        system->kernelBinning->execute(xcProxy, inst);
+        system->kernelBinning->execute(tc, inst);
     }
 
     if (cpuXC->profile) {
         bool usermode =
             (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
         cpuXC->profilePC = usermode ? 1 : cpuXC->readPC();
-        ProfileNode *node = cpuXC->profile->consume(xcProxy, inst);
+        ProfileNode *node = cpuXC->profile->consume(tc, inst);
         if (node)
             cpuXC->profileNode = node;
     }
@@ -446,7 +446,7 @@ BaseSimpleCPU::advancePC(Fault fault)
 {
     if (fault != NoFault) {
 #if FULL_SYSTEM
-        fault->invoke(xcProxy);
+        fault->invoke(tc);
 #else // !FULL_SYSTEM
         fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC());
 #endif // FULL_SYSTEM
@@ -467,7 +467,7 @@ BaseSimpleCPU::advancePC(Fault fault)
     Addr oldpc;
     do {
         oldpc = cpuXC->readPC();
-        system->pcEventQueue.service(xcProxy);
+        system->pcEventQueue.service(tc);
     } while (oldpc != cpuXC->readPC());
 #endif
 }
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index e7d90f95d..bc17ece56 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -61,7 +61,7 @@ class Process;
 
 #endif // FULL_SYSTEM
 
-class ExecContext;
+class ThreadContext;
 class Checkpoint;
 
 namespace Trace {
@@ -111,7 +111,7 @@ class BaseSimpleCPU : public BaseCPU
     // execution context
     CPUExecContext *cpuXC;
 
-    ExecContext *xcProxy;
+    ThreadContext *tc;
 
 #if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
@@ -307,14 +307,14 @@ class BaseSimpleCPU : public BaseCPU
     int readIntrFlag() { return cpuXC->readIntrFlag(); }
     void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
     bool inPalMode() { return cpuXC->inPalMode(); }
-    void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
+    void ev5_trap(Fault fault) { fault->invoke(tc); }
     bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
 #else
     void syscall(int64_t callnum) { cpuXC->syscall(callnum); }
 #endif
 
     bool misspeculating() { return cpuXC->misspeculating(); }
-    ExecContext *xcBase() { return xcProxy; }
+    ThreadContext *tcBase() { return tc; }
 };
 
 #endif // __CPU_SIMPLE_BASE_HH__
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 1e5a628c7..00c6de037 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -52,11 +52,11 @@ TimingSimpleCPU::init()
 
     BaseCPU::init();
 #if FULL_SYSTEM
-    for (int i = 0; i < execContexts.size(); ++i) {
-        ExecContext *xc = execContexts[i];
+    for (int i = 0; i < threadContexts.size(); ++i) {
+        ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(xc, xc->readCpuId());
+        TheISA::initCPU(tc, tc->readCpuId());
     }
 #endif
 }
@@ -125,11 +125,11 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 {
     BaseCPU::takeOverFrom(oldCPU);
 
-    // if any of this CPU's ExecContexts are active, mark the CPU as
+    // if any of this CPU's ThreadContexts are active, mark the CPU as
     // running and schedule its tick event.
-    for (int i = 0; i < execContexts.size(); ++i) {
-        ExecContext *xc = execContexts[i];
-        if (xc->status() == ExecContext::Active && _status != Running) {
+    for (int i = 0; i < threadContexts.size(); ++i) {
+        ThreadContext *tc = threadContexts[i];
+        if (tc->status() == ThreadContext::Active && _status != Running) {
             _status = Running;
             break;
         }
diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc
index 86517a5f4..c311d2282 100644
--- a/src/cpu/static_inst.cc
+++ b/src/cpu/static_inst.cc
@@ -60,7 +60,7 @@ StaticInst::dumpDecodeCacheStats()
 }
 
 bool
-StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
+StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const
 {
     if (isDirectCtrl()) {
         tgt = branchTarget(pc);
@@ -68,7 +68,7 @@ StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
     }
 
     if (isIndirectCtrl()) {
-        tgt = branchTarget(xc);
+        tgt = branchTarget(tc);
         return true;
     }
 
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 6f6cf45da..bea52f510 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -45,7 +45,7 @@
 struct AlphaSimpleImpl;
 struct OzoneImpl;
 struct SimpleImpl;
-class ExecContext;
+class ThreadContext;
 class DynInst;
 class Packet;
 
@@ -357,12 +357,12 @@ class StaticInst : public StaticInstBase
 
     /**
      * Return the target address for an indirect branch (jump).  The
-     * register value is read from the supplied execution context, so
-     * the result is valid only if the execution context is about to
+     * register value is read from the supplied thread context, so
+     * the result is valid only if the thread context is about to
      * execute the branch in question.  Invalid if not an indirect
      * branch (i.e. isIndirectCtrl() should be true).
      */
-    virtual Addr branchTarget(ExecContext *xc) const
+    virtual Addr branchTarget(ThreadContext *tc) const
     {
         panic("StaticInst::branchTarget() called on instruction "
               "that is not an indirect branch.");
@@ -372,7 +372,7 @@ class StaticInst : public StaticInstBase
      * Return true if the instruction is a control transfer, and if so,
      * return the target address as well.
      */
-    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
+    bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
 
     /**
      * Return string representation of disassembled instruction.
diff --git a/src/cpu/exec_context.hh b/src/cpu/thread_context.hh
index c9a060b0b..ac2b44ba8 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/thread_context.hh
@@ -28,8 +28,8 @@
  * Authors: Kevin Lim
  */
 
-#ifndef __CPU_EXEC_CONTEXT_HH__
-#define __CPU_EXEC_CONTEXT_HH__
+#ifndef __CPU_THREAD_CONTEXT_HH__
+#define __CPU_THREAD_CONTEXT_HH__
 
 #include "config/full_system.hh"
 #include "mem/request.hh"
@@ -54,7 +54,23 @@ namespace Kernel {
     class Statistics;
 };
 
-class ExecContext
+/**
+ * ThreadContext is the external interface to all thread state for
+ * anything outside of the CPU. It provides all accessor methods to
+ * state that might be needed by external objects, ranging from
+ * register values to things such as kernel stats. It is an abstract
+ * base class; the CPU can create its own ThreadContext by either
+ * deriving from it, or using the templated ProxyThreadContext.
+ *
+ * The ThreadContext is slightly different than the ExecContext.  The
+ * ThreadContext provides access to an individual thread's state; an
+ * ExecContext provides ISA access to the CPU (meaning it is
+ * implicitly multithreaded on MT systems).  Additionally the
+ * ThreadState is an abstract class that exactly defines the
+ * interface; the ExecContext is a more implicit interface that must
+ * be implemented so that the ISA can access whatever state it needs.
+ */
+class ThreadContext
 {
   protected:
     typedef TheISA::RegFile RegFile;
@@ -87,7 +103,7 @@ class ExecContext
         Halted
     };
 
-    virtual ~ExecContext() { };
+    virtual ~ThreadContext() { };
 
     virtual BaseCPU *getCpuPtr() = 0;
 
@@ -106,7 +122,7 @@ class ExecContext
 
     virtual FunctionalPort *getPhysPort() = 0;
 
-    virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0;
+    virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
 
     virtual void delVirtPort(VirtualPort *vp) = 0;
 #else
@@ -136,7 +152,7 @@ class ExecContext
     virtual void dumpFuncProfile() = 0;
 #endif
 
-    virtual void takeOverFrom(ExecContext *old_context) = 0;
+    virtual void takeOverFrom(ThreadContext *old_context) = 0;
 
     virtual void regStats(const std::string &name) = 0;
 
@@ -161,7 +177,7 @@ class ExecContext
     // However, may be quite useful in SPARC.
     virtual TheISA::MachInst getInst() = 0;
 
-    virtual void copyArchRegs(ExecContext *xc) = 0;
+    virtual void copyArchRegs(ThreadContext *tc) = 0;
 
     virtual void clearArchRegs() = 0;
 
@@ -238,181 +254,181 @@ class ExecContext
             RegFile::ContextVal val) = 0;
 };
 
-template <class XC>
-class ProxyExecContext : public ExecContext
+template <class TC>
+class ProxyThreadContext : public ThreadContext
 {
   public:
-    ProxyExecContext(XC *actual_xc)
-    { actualXC = actual_xc; }
+    ProxyThreadContext(TC *actual_tc)
+    { actualTC = actual_tc; }
 
   private:
-    XC *actualXC;
+    TC *actualTC;
 
   public:
 
-    BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
+    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 
-    void setCpuId(int id) { actualXC->setCpuId(id); }
+    void setCpuId(int id) { actualTC->setCpuId(id); }
 
-    int readCpuId() { return actualXC->readCpuId(); }
+    int readCpuId() { return actualTC->readCpuId(); }
 
 #if FULL_SYSTEM
-    System *getSystemPtr() { return actualXC->getSystemPtr(); }
+    System *getSystemPtr() { return actualTC->getSystemPtr(); }
 
-    AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
+    AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
 
-    AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
+    AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
-    Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); }
+    Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
 
-    FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); }
+    FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
 
-    VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); }
+    VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
 
-    void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); }
+    void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
 #else
-    TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
+    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
 
-    Process *getProcessPtr() { return actualXC->getProcessPtr(); }
+    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
 #endif
 
-    Status status() const { return actualXC->status(); }
+    Status status() const { return actualTC->status(); }
 
-    void setStatus(Status new_status) { actualXC->setStatus(new_status); }
+    void setStatus(Status new_status) { actualTC->setStatus(new_status); }
 
     /// Set the status to Active.  Optional delay indicates number of
     /// cycles to wait before beginning execution.
-    void activate(int delay = 1) { actualXC->activate(delay); }
+    void activate(int delay = 1) { actualTC->activate(delay); }
 
     /// Set the status to Suspended.
-    void suspend() { actualXC->suspend(); }
+    void suspend() { actualTC->suspend(); }
 
     /// Set the status to Unallocated.
-    void deallocate() { actualXC->deallocate(); }
+    void deallocate() { actualTC->deallocate(); }
 
     /// Set the status to Halted.
-    void halt() { actualXC->halt(); }
+    void halt() { actualTC->halt(); }
 
 #if FULL_SYSTEM
-    void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
+    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
 #endif
 
-    void takeOverFrom(ExecContext *oldContext)
-    { actualXC->takeOverFrom(oldContext); }
+    void takeOverFrom(ThreadContext *oldContext)
+    { actualTC->takeOverFrom(oldContext); }
 
-    void regStats(const std::string &name) { actualXC->regStats(name); }
+    void regStats(const std::string &name) { actualTC->regStats(name); }
 
-    void serialize(std::ostream &os) { actualXC->serialize(os); }
+    void serialize(std::ostream &os) { actualTC->serialize(os); }
     void unserialize(Checkpoint *cp, const std::string &section)
-    { actualXC->unserialize(cp, section); }
+    { actualTC->unserialize(cp, section); }
 
 #if FULL_SYSTEM
-    EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
+    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 
-    Tick readLastActivate() { return actualXC->readLastActivate(); }
-    Tick readLastSuspend() { return actualXC->readLastSuspend(); }
+    Tick readLastActivate() { return actualTC->readLastActivate(); }
+    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
 
-    void profileClear() { return actualXC->profileClear(); }
-    void profileSample() { return actualXC->profileSample(); }
+    void profileClear() { return actualTC->profileClear(); }
+    void profileSample() { return actualTC->profileSample(); }
 #endif
 
-    int getThreadNum() { return actualXC->getThreadNum(); }
+    int getThreadNum() { return actualTC->getThreadNum(); }
 
     // @todo: Do I need this?
-    MachInst getInst() { return actualXC->getInst(); }
+    MachInst getInst() { return actualTC->getInst(); }
 
     // @todo: Do I need this?
-    void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); }
+    void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
 
-    void clearArchRegs() { actualXC->clearArchRegs(); }
+    void clearArchRegs() { actualTC->clearArchRegs(); }
 
     //
     // New accessors for new decoder.
     //
     uint64_t readIntReg(int reg_idx)
-    { return actualXC->readIntReg(reg_idx); }
+    { return actualTC->readIntReg(reg_idx); }
 
     FloatReg readFloatReg(int reg_idx, int width)
-    { return actualXC->readFloatReg(reg_idx, width); }
+    { return actualTC->readFloatReg(reg_idx, width); }
 
     FloatReg readFloatReg(int reg_idx)
-    { return actualXC->readFloatReg(reg_idx); }
+    { return actualTC->readFloatReg(reg_idx); }
 
     FloatRegBits readFloatRegBits(int reg_idx, int width)
-    { return actualXC->readFloatRegBits(reg_idx, width); }
+    { return actualTC->readFloatRegBits(reg_idx, width); }
 
     FloatRegBits readFloatRegBits(int reg_idx)
-    { return actualXC->readFloatRegBits(reg_idx); }
+    { return actualTC->readFloatRegBits(reg_idx); }
 
     void setIntReg(int reg_idx, uint64_t val)
-    { actualXC->setIntReg(reg_idx, val); }
+    { actualTC->setIntReg(reg_idx, val); }
 
     void setFloatReg(int reg_idx, FloatReg val, int width)
-    { actualXC->setFloatReg(reg_idx, val, width); }
+    { actualTC->setFloatReg(reg_idx, val, width); }
 
     void setFloatReg(int reg_idx, FloatReg val)
-    { actualXC->setFloatReg(reg_idx, val); }
+    { actualTC->setFloatReg(reg_idx, val); }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-    { actualXC->setFloatRegBits(reg_idx, val, width); }
+    { actualTC->setFloatRegBits(reg_idx, val, width); }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val)
-    { actualXC->setFloatRegBits(reg_idx, val); }
+    { actualTC->setFloatRegBits(reg_idx, val); }
 
-    uint64_t readPC() { return actualXC->readPC(); }
+    uint64_t readPC() { return actualTC->readPC(); }
 
-    void setPC(uint64_t val) { actualXC->setPC(val); }
+    void setPC(uint64_t val) { actualTC->setPC(val); }
 
-    uint64_t readNextPC() { return actualXC->readNextPC(); }
+    uint64_t readNextPC() { return actualTC->readNextPC(); }
 
-    void setNextPC(uint64_t val) { actualXC->setNextPC(val); }
+    void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
 
-    uint64_t readNextNPC() { return actualXC->readNextNPC(); }
+    uint64_t readNextNPC() { return actualTC->readNextNPC(); }
 
-    void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); }
+    void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
 
     MiscReg readMiscReg(int misc_reg)
-    { return actualXC->readMiscReg(misc_reg); }
+    { return actualTC->readMiscReg(misc_reg); }
 
     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
-    { return actualXC->readMiscRegWithEffect(misc_reg, fault); }
+    { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
 
     Fault setMiscReg(int misc_reg, const MiscReg &val)
-    { return actualXC->setMiscReg(misc_reg, val); }
+    { return actualTC->setMiscReg(misc_reg, val); }
 
     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
-    { return actualXC->setMiscRegWithEffect(misc_reg, val); }
+    { return actualTC->setMiscRegWithEffect(misc_reg, val); }
 
     unsigned readStCondFailures()
-    { return actualXC->readStCondFailures(); }
+    { return actualTC->readStCondFailures(); }
 
     void setStCondFailures(unsigned sc_failures)
-    { actualXC->setStCondFailures(sc_failures); }
+    { actualTC->setStCondFailures(sc_failures); }
 #if FULL_SYSTEM
-    bool inPalMode() { return actualXC->inPalMode(); }
+    bool inPalMode() { return actualTC->inPalMode(); }
 #endif
 
     // @todo: Fix this!
-    bool misspeculating() { return actualXC->misspeculating(); }
+    bool misspeculating() { return actualTC->misspeculating(); }
 
 #if !FULL_SYSTEM
-    IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
+    IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, IntReg val)
-    { actualXC->setSyscallArg(i, val); }
+    { actualTC->setSyscallArg(i, val); }
 
     void setSyscallReturn(SyscallReturn return_value)
-    { actualXC->setSyscallReturn(return_value); }
+    { actualTC->setSyscallReturn(return_value); }
 
 
-    Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
+    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 #endif
 
     void changeRegFileContext(RegFile::ContextParam param,
             RegFile::ContextVal val)
     {
-        actualXC->changeRegFileContext(param, val);
+        actualTC->changeRegFileContext(param, val);
     }
 };
 
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index a96884d5b..6d64c94f7 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -29,7 +29,7 @@
 #ifndef __CPU_THREAD_STATE_HH__
 #define __CPU_THREAD_STATE_HH__
 
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 
 #if !FULL_SYSTEM
 #include "mem/translating_port.hh"
@@ -78,7 +78,7 @@ struct ThreadState {
 #endif
     }
 
-    ExecContext::Status status;
+    ThreadContext::Status status;
 
     int cpuId;