summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2008-10-12 19:32:06 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-12 19:32:06 -0700
commit0756dbb37a432b895b019e49862fcd7f42e1bd00 (patch)
tree65150c5322fb875b3766c4d876a13dfb828df060 /src/cpu
parentf245358343fb26ac976d15b8f2a023caa0f9ba0d (diff)
downloadgem5-0756dbb37a432b895b019e49862fcd7f42e1bd00.tar.xz
X86: Don't fetch in the simple CPU if you're in the ROM.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/simple/atomic.cc40
-rw-r--r--src/cpu/simple/timing.cc56
2 files changed, 57 insertions, 39 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 154a66162..878f69f0c 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -718,31 +718,37 @@ AtomicSimpleCPU::tick()
checkPcEventQueue();
- Fault fault = setupFetchRequest(&ifetch_req);
+ Fault fault = NoFault;
+
+ bool fromRom = isRomMicroPC(thread->readMicroPC());
+ if (!fromRom)
+ fault = setupFetchRequest(&ifetch_req);
if (fault == NoFault) {
Tick icache_latency = 0;
bool icache_access = false;
dcache_access = false; // assume no dcache access
- //Fetch more instruction memory if necessary
- //if(predecoder.needMoreBytes())
- //{
- icache_access = true;
- Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
- Packet::Broadcast);
- ifetch_pkt.dataStatic(&inst);
-
- if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
- icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
- else
- icache_latency = icachePort.sendAtomic(&ifetch_pkt);
+ if (!fromRom) {
+ //Fetch more instruction memory if necessary
+ //if(predecoder.needMoreBytes())
+ //{
+ icache_access = true;
+ Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
+ Packet::Broadcast);
+ ifetch_pkt.dataStatic(&inst);
+
+ if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
+ icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
+ else
+ icache_latency = icachePort.sendAtomic(&ifetch_pkt);
- assert(!ifetch_pkt.isError());
+ assert(!ifetch_pkt.isError());
- // ifetch_req is initialized to read the instruction directly
- // into the CPU object's inst field.
- //}
+ // ifetch_req is initialized to read the instruction directly
+ // into the CPU object's inst field.
+ //}
+ }
preExecute();
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index c4635d6a3..0cda9a0a3 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -531,28 +531,35 @@ TimingSimpleCPU::fetch()
checkPcEventQueue();
- Request *ifetch_req = new Request();
- ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
- Fault fault = setupFetchRequest(ifetch_req);
+ bool fromRom = isRomMicroPC(thread->readMicroPC());
- ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
- ifetch_pkt->dataStatic(&inst);
+ if (!fromRom) {
+ Request *ifetch_req = new Request();
+ ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
+ Fault fault = setupFetchRequest(ifetch_req);
- if (fault == NoFault) {
- if (!icachePort.sendTiming(ifetch_pkt)) {
- // Need to wait for retry
- _status = IcacheRetry;
+ ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
+ ifetch_pkt->dataStatic(&inst);
+
+ if (fault == NoFault) {
+ if (!icachePort.sendTiming(ifetch_pkt)) {
+ // Need to wait for retry
+ _status = IcacheRetry;
+ } else {
+ // Need to wait for cache to respond
+ _status = IcacheWaitResponse;
+ // ownership of packet transferred to memory system
+ ifetch_pkt = NULL;
+ }
} else {
- // Need to wait for cache to respond
- _status = IcacheWaitResponse;
- // ownership of packet transferred to memory system
- ifetch_pkt = NULL;
+ delete ifetch_req;
+ delete ifetch_pkt;
+ // fetch fault: advance directly to next instruction (fault handler)
+ advanceInst(fault);
}
} else {
- delete ifetch_req;
- delete ifetch_pkt;
- // fetch fault: advance directly to next instruction (fault handler)
- advanceInst(fault);
+ _status = IcacheWaitResponse;
+ completeIfetch(NULL);
}
numCycles += tickToCycles(curTick - previousTick);
@@ -581,7 +588,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
// received a response from the icache: execute the received
// instruction
- assert(!pkt->isError());
+
+ assert(!pkt || !pkt->isError());
assert(_status == IcacheWaitResponse);
_status = Running;
@@ -590,8 +598,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
previousTick = curTick;
if (getState() == SimObject::Draining) {
- delete pkt->req;
- delete pkt;
+ if (pkt) {
+ delete pkt->req;
+ delete pkt;
+ }
completeDrain();
return;
@@ -658,8 +668,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
advanceInst(fault);
}
- delete pkt->req;
- delete pkt;
+ if (pkt) {
+ delete pkt->req;
+ delete pkt;
+ }
}
void