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authorKorey Sewell <ksewell@umich.edu>2010-01-31 18:29:59 -0500
committerKorey Sewell <ksewell@umich.edu>2010-01-31 18:29:59 -0500
commit1a89e8f4cbab3b3a6fd144d3d08dfeaac203f945 (patch)
tree35cf98061afa705a55ab84a7bed1e51aa89b65ec /src/cpu
parent002f1b8b7e1d5292828e5157ff971965265140bc (diff)
downloadgem5-1a89e8f4cbab3b3a6fd144d3d08dfeaac203f945.tar.xz
inorder: user per-thread dummy insts/reqs
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/inorder/cpu.cc35
-rw-r--r--src/cpu/inorder/cpu.hh7
-rw-r--r--src/cpu/inorder/resource_pool.cc5
-rw-r--r--src/cpu/inorder/resource_pool.hh3
4 files changed, 30 insertions, 20 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index b69fe2e3b..472317362 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -211,6 +211,7 @@ InOrderCPU::InOrderCPU(Params *params)
"edit your workload size.");
}
+
if (active_threads > 1) {
threadModel = (InOrderCPU::ThreadModel) params->threadModel;
@@ -257,6 +258,9 @@ InOrderCPU::InOrderCPU(Params *params)
Process* dummy_proc = params->workload[0];
thread[tid] = new Thread(this, tid, dummy_proc);
}
+
+ // Eventually set this with parameters...
+ asid[tid] = tid;
#endif
// Setup the TC that will serve as the interface to the threads/CPU.
@@ -313,14 +317,24 @@ InOrderCPU::InOrderCPU(Params *params)
isa[tid].clear();
isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
+
+ // Define dummy instructions and resource requests to be used.
+ dummyInst[tid] = new InOrderDynInst(this,
+ thread[tid],
+ 0,
+ tid,
+ asid[tid]);
+
+ dummyReq[tid] = new ResourceRequest(resPool->getResource(0),
+ dummyInst[tid],
+ 0,
+ 0,
+ 0,
+ 0);
}
lastRunningCycle = curTick;
- // Define dummy instructions and resource requests to be used.
- dummyInst = new InOrderDynInst(this, NULL, 0, 0);
- dummyReq = new ResourceRequest(resPool->getResource(0), NULL, 0, 0, 0, 0);
-
// Reset CPU to reset state.
#if FULL_SYSTEM
Fault resetFault = new ResetFault();
@@ -585,7 +599,7 @@ void
InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
{
//@ Squash Pipeline during TRAP
- scheduleCpuEvent(Trap, fault, tid, dummyInst, delay);
+ scheduleCpuEvent(Trap, fault, tid, dummyInst[tid], delay);
}
void
@@ -747,7 +761,7 @@ InOrderCPU::deactivateContext(ThreadID tid, int delay)
{
DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
- scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst, delay);
+ scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
// Be sure to signal that there's some activity so the CPU doesn't
// deschedule itself.
@@ -830,7 +844,8 @@ InOrderCPU::activateContext(ThreadID tid, int delay)
{
DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
- scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst, delay);
+
+ scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
// Be sure to signal that there's some activity so the CPU doesn't
// deschedule itself.
@@ -847,7 +862,7 @@ InOrderCPU::activateNextReadyContext(int delay)
// NOTE: Add 5 to the event priority so that we always activate
// threads after we've finished deactivating, squashing,etc.
// other threads
- scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst,
+ scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
delay, 5);
// Be sure to signal that there's some activity so the CPU doesn't
@@ -862,7 +877,7 @@ InOrderCPU::haltContext(ThreadID tid, int delay)
{
DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
- scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst, delay);
+ scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
activityRec.activity();
}
@@ -885,7 +900,7 @@ InOrderCPU::haltThread(ThreadID tid)
void
InOrderCPU::suspendContext(ThreadID tid, int delay)
{
- scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst, delay);
+ scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
}
void
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 6f1f3ee3f..dc0164d8f 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -97,6 +97,9 @@ class InOrderCPU : public BaseCPU
/** CPU ID */
int cpu_id;
+ // SE Mode ASIDs
+ ThreadID asid[ThePipeline::MaxThreads];
+
/** Type of core that this is */
std::string coreType;
@@ -241,10 +244,10 @@ class InOrderCPU : public BaseCPU
/** Instruction used to signify that there is no *real* instruction in
buffer slot */
- DynInstPtr dummyInst;
+ DynInstPtr dummyInst[ThePipeline::MaxThreads];
/** Used by resources to signify a denied access to a resource. */
- ResourceRequest *dummyReq;
+ ResourceRequest *dummyReq[ThePipeline::MaxThreads];
/** Identifies the resource id that identifies a fetch
* access unit.
diff --git a/src/cpu/inorder/resource_pool.cc b/src/cpu/inorder/resource_pool.cc
index 3750d18d6..dd51242a3 100644
--- a/src/cpu/inorder/resource_pool.cc
+++ b/src/cpu/inorder/resource_pool.cc
@@ -448,11 +448,6 @@ ResourcePool::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
}
}
-ResourcePool::ResPoolEvent::ResPoolEvent(ResourcePool *_resPool)
- : Event((Event::Priority)((unsigned)CPU_Tick_Pri+5)), resPool(_resPool),
- eventType((InOrderCPU::CPUEventType) Default)
-{ }
-
ResourcePool::ResPoolEvent::ResPoolEvent(ResourcePool *_resPool,
InOrderCPU::CPUEventType e_type,
DynInstPtr _inst,
diff --git a/src/cpu/inorder/resource_pool.hh b/src/cpu/inorder/resource_pool.hh
index 3f62d2caa..f61fae4c8 100644
--- a/src/cpu/inorder/resource_pool.hh
+++ b/src/cpu/inorder/resource_pool.hh
@@ -86,9 +86,6 @@ class ResourcePool {
public:
/** Constructs a resource event. */
- ResPoolEvent(ResourcePool *_resPool);
-
- /** Constructs a resource event. */
ResPoolEvent(ResourcePool *_resPool,
InOrderCPU::CPUEventType e_type,
DynInstPtr _inst,