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authorGabe Black <gblack@eecs.umich.edu>2008-11-09 21:55:01 -0800
committerGabe Black <gblack@eecs.umich.edu>2008-11-09 21:55:01 -0800
commit909380f3ee576f915f52c6245c59d41050a46f49 (patch)
treeaafb5d6cbc656fcf2d66fd62da7db657e75cb1be /src/cpu
parent72743e5020acb671bdd8a4a285ead308859f2605 (diff)
downloadgem5-909380f3ee576f915f52c6245c59d41050a46f49.tar.xz
X86: Make the timing simple CPU handle variable length instructions.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/simple/timing.cc10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ca1f0283e..f5eeeba60 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -561,7 +561,8 @@ TimingSimpleCPU::fetch()
void
TimingSimpleCPU::advanceInst(Fault fault)
{
- advancePC(fault);
+ if (fault != NoFault || !stayAtPC)
+ advancePC(fault);
if (_status == Running) {
// kick off fetch of next instruction... callback from icache
@@ -599,7 +600,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
}
preExecute();
- if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
+ if (curStaticInst &&
+ curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
// load or store: just send to dcache
Fault fault = curStaticInst->initiateAcc(this, traceData);
if (_status != Running) {
@@ -638,7 +640,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
instCnt++;
advanceInst(fault);
}
- } else {
+ } else if (curStaticInst) {
// non-memory instruction: execute completely now
Fault fault = curStaticInst->execute(this, traceData);
@@ -657,6 +659,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
curStaticInst->isFirstMicroop()))
instCnt++;
advanceInst(fault);
+ } else {
+ advanceInst(NoFault);
}
if (pkt) {