O3: Generaize the O3 IMPL class so it isn't split out by ISA.

--HG--
rename : src/cpu/o3/sparc/cpu_builder.cc => src/cpu/o3/cpu_builder.cc
rename : src/cpu/o3/sparc/dyn_inst.cc => src/cpu/o3/dyn_inst.cc
rename : src/cpu/o3/sparc/impl.hh => src/cpu/o3/impl.hh
rename : src/cpu/o3/sparc/thread_context.cc => src/cpu/o3/thread_context.cc

19 files changed, 24 insertions, 692 deletions

diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index 2de106d8b..f05986bf5 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -51,7 +51,9 @@ if 'O3CPU' in env['CPU_MODELS']:
     Source('bpred_unit.cc')
     Source('commit.cc')
     Source('cpu.cc')
+    Source('cpu_builder.cc')
     Source('decode.cc')
+    Source('dyn_inst.cc')
     Source('fetch.cc')
     Source('free_list.cc')
     Source('fu_pool.cc')
@@ -65,6 +67,7 @@ if 'O3CPU' in env['CPU_MODELS']:
     Source('rob.cc')
     Source('scoreboard.cc')
     Source('store_set.cc')
+    Source('thread_context.cc')
 
     TraceFlag('FreeList')
     TraceFlag('LSQ')
@@ -81,24 +84,6 @@ if 'O3CPU' in env['CPU_MODELS']:
         'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
         'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
 
-    if env['TARGET_ISA'] == 'alpha':
-        Source('alpha/cpu.cc')
-        Source('alpha/cpu_builder.cc')
-        Source('alpha/dyn_inst.cc')
-        Source('alpha/thread_context.cc')
-    elif env['TARGET_ISA'] == 'mips':
-        Source('mips/cpu.cc')
-        Source('mips/cpu_builder.cc')
-        Source('mips/dyn_inst.cc')
-        Source('mips/thread_context.cc')
-    elif env['TARGET_ISA'] == 'sparc':
-        Source('sparc/cpu.cc')
-        Source('sparc/cpu_builder.cc')
-        Source('sparc/dyn_inst.cc')
-        Source('sparc/thread_context.cc')
-    else:
-        sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
-
     if env['USE_CHECKER']:
         SimObject('O3Checker.py')
         Source('checker_builder.cc')
diff --git a/src/cpu/o3/alpha/cpu.cc b/src/cpu/o3/alpha/cpu.cc
deleted file mode 100644
index 740e6476d..000000000
--- a/src/cpu/o3/alpha/cpu.cc
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#include "cpu/o3/alpha/impl.hh"
-#include "cpu/o3/cpu.hh"
-
-// Force instantiation of AlphaO3CPU for all the implemntations that are
-// needed.  Consider merging this and alpha_dyn_inst.cc, and maybe all
-// classes that depend on a certain impl, into one file (alpha_impl.cc?).
-template class FullO3CPU<AlphaSimpleImpl>;
diff --git a/src/cpu/o3/alpha/dyn_inst.cc b/src/cpu/o3/alpha/dyn_inst.cc
deleted file mode 100644
index 28e70be8a..000000000
--- a/src/cpu/o3/alpha/dyn_inst.cc
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#include "cpu/o3/alpha/impl.hh"
-#include "cpu/o3/dyn_inst_impl.hh"
-
-// Force instantiation of AlphaDynInst for all the implementations that
-// are needed.
-template class BaseO3DynInst<AlphaSimpleImpl>;
diff --git a/src/cpu/o3/alpha/impl.hh b/src/cpu/o3/alpha/impl.hh
deleted file mode 100644
index 7d956cd6a..000000000
--- a/src/cpu/o3/alpha/impl.hh
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_O3_ALPHA_IMPL_HH__
-#define __CPU_O3_ALPHA_IMPL_HH__
-
-#include "arch/alpha/isa_traits.hh"
-
-#include "cpu/o3/cpu_policy.hh"
-
-
-// Forward declarations.
-template <class Impl>
-class BaseO3DynInst;
-
-template <class Impl>
-class FullO3CPU;
-
-/** Implementation specific struct that defines several key types to the
- *  CPU, the stages within the CPU, the time buffers, and the DynInst.
- *  The struct defines the ISA, the CPU policy, the specific DynInst, the
- *  specific O3CPU, and all of the structs from the time buffers to do
- *  communication.
- *  This is one of the key things that must be defined for each hardware
- *  specific CPU implementation.
- */
-struct AlphaSimpleImpl
-{
-    /** The type of MachInst. */
-    typedef TheISA::MachInst MachInst;
-
-    /** The CPU policy to be used, which defines all of the CPU stages. */
-    typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
-
-    /** The DynInst type to be used. */
-    typedef BaseO3DynInst<AlphaSimpleImpl> DynInst;
-
-    /** The refcounted DynInst pointer to be used.  In most cases this is
-     *  what should be used, and not DynInst *.
-     */
-    typedef RefCountingPtr<DynInst> DynInstPtr;
-
-    /** The O3CPU type to be used. */
-    typedef FullO3CPU<AlphaSimpleImpl> O3CPU;
-
-    /** Same typedef, but for CPUType.  BaseDynInst may not always use
-     * an O3 CPU, so it's clearer to call it CPUType instead in that
-     * case.
-     */
-    typedef O3CPU CPUType;
-
-    enum {
-      MaxWidth = 8,
-      MaxThreads = 4
-    };
-};
-
-/** The O3Impl to be used. */
-typedef AlphaSimpleImpl O3CPUImpl;
-
-#endif // __CPU_O3_ALPHA_IMPL_HH__
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/cpu_builder.cc
index deeb437be..77d7091ad 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/cpu_builder.cc
@@ -33,14 +33,14 @@
 #include "config/full_system.hh"
 #include "config/use_checker.hh"
 #include "cpu/o3/cpu.hh"
-#include "cpu/o3/alpha/impl.hh"
+#include "cpu/o3/impl.hh"
 #include "params/DerivO3CPU.hh"
 
-class DerivO3CPU : public FullO3CPU<AlphaSimpleImpl>
+class DerivO3CPU : public FullO3CPU<O3CPUImpl>
 {
   public:
     DerivO3CPU(DerivO3CPUParams *p)
-        : FullO3CPU<AlphaSimpleImpl>(p)
+        : FullO3CPU<O3CPUImpl>(p)
     { }
 };
 
diff --git a/src/cpu/o3/sparc/dyn_inst.cc b/src/cpu/o3/dyn_inst.cc
index ea86f8719..d828ef1b0 100644
--- a/src/cpu/o3/sparc/dyn_inst.cc
+++ b/src/cpu/o3/dyn_inst.cc
@@ -29,8 +29,8 @@
  */
 
 #include "cpu/o3/dyn_inst_impl.hh"
-#include "cpu/o3/sparc/impl.hh"
+#include "cpu/o3/impl.hh"
 
-// Force instantiation of SparcDynInst for all the implementations that
+// Force instantiation of BaseO3DynInst for all the implementations that
 // are needed.
-template class BaseO3DynInst<SparcSimpleImpl>;
+template class BaseO3DynInst<O3CPUImpl>;
diff --git a/src/cpu/o3/dyn_inst_decl.hh b/src/cpu/o3/dyn_inst_decl.hh
deleted file mode 100644
index 750c3279d..000000000
--- a/src/cpu/o3/dyn_inst_decl.hh
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
- */
-
-#ifndef __CPU_O3_DYN_INST_DECL_HH__
-#define __CPU_O3_DYN_INST_DECL_HH__
-
-#include "arch/isa_specific.hh"
-
-template <class Impl> class BaseO3DynInst;
-#if THE_ISA == ALPHA_ISA
-    struct AlphaSimpleImpl;
-    typedef BaseO3DynInst<AlphaSimpleImpl> O3DynInst;
-#elif THE_ISA == MIPS_ISA
-    struct MipsSimpleImpl;
-    typedef BaseO3DynInst<MipsSimpleImpl> O3DynInst;
-#elif THE_ISA == SPARC_ISA
-    struct SparcSimpleImpl;
-    typedef BaseO3DynInst<SparcSimpleImpl> O3DynInst;
-#elif THE_ISA == X86_ISA
-    struct X86SimpleImpl;
-    typedef BaseO3DynInst<X86SimpleImpl> O3DynInst;
-#elif THE_ISA == ARM_ISA
-    struct ArmSimpleImpl;
-    typedef BaseO3DynInst<ArmSimpleImpl> O3DynInst;
-#else
-    #error "O3DynInst not defined for this ISA"
-#endif
-
-#endif // __CPU_O3_DYN_INST_DECL_HH__
diff --git a/src/cpu/o3/sparc/impl.hh b/src/cpu/o3/impl.hh
index cf0e33e42..4b29b4daa 100644
--- a/src/cpu/o3/sparc/impl.hh
+++ b/src/cpu/o3/impl.hh
@@ -25,13 +25,13 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Gabe Black
+ * Authors: Kevin Lim
  */
 
-#ifndef __CPU_O3_SPARC_IMPL_HH__
-#define __CPU_O3_SPARC_IMPL_HH__
+#ifndef __CPU_O3_IMPL_HH__
+#define __CPU_O3_IMPL_HH__
 
-#include "arch/sparc/isa_traits.hh"
+#include "arch/isa_traits.hh"
 
 #include "cpu/o3/cpu_policy.hh"
 
@@ -51,16 +51,16 @@ class FullO3CPU;
  *  This is one of the key things that must be defined for each hardware
  *  specific CPU implementation.
  */
-struct SparcSimpleImpl
+struct O3CPUImpl
 {
     /** The type of MachInst. */
     typedef TheISA::MachInst MachInst;
 
     /** The CPU policy to be used, which defines all of the CPU stages. */
-    typedef SimpleCPUPolicy<SparcSimpleImpl> CPUPol;
+    typedef SimpleCPUPolicy<O3CPUImpl> CPUPol;
 
     /** The DynInst type to be used. */
-    typedef BaseO3DynInst<SparcSimpleImpl> DynInst;
+    typedef BaseO3DynInst<O3CPUImpl> DynInst;
 
     /** The refcounted DynInst pointer to be used.  In most cases this is
      *  what should be used, and not DynInst *.
@@ -68,7 +68,7 @@ struct SparcSimpleImpl
     typedef RefCountingPtr<DynInst> DynInstPtr;
 
     /** The O3CPU type to be used. */
-    typedef FullO3CPU<SparcSimpleImpl> O3CPU;
+    typedef FullO3CPU<O3CPUImpl> O3CPU;
 
     /** Same typedef, but for CPUType.  BaseDynInst may not always use
      * an O3 CPU, so it's clearer to call it CPUType instead in that
@@ -82,7 +82,4 @@ struct SparcSimpleImpl
     };
 };
 
-/** The O3Impl to be used. */
-typedef SparcSimpleImpl O3CPUImpl;
-
 #endif // __CPU_O3_SPARC_IMPL_HH__
diff --git a/src/cpu/o3/isa_specific.hh b/src/cpu/o3/isa_specific.hh
index 6111a5336..e9347af91 100755
--- a/src/cpu/o3/isa_specific.hh
+++ b/src/cpu/o3/isa_specific.hh
@@ -30,13 +30,5 @@
 
 #include "cpu/base.hh"
 
-#if THE_ISA == ALPHA_ISA
-    #include "cpu/o3/alpha/impl.hh"
-#elif THE_ISA == MIPS_ISA
-    #include "cpu/o3/mips/impl.hh"
-#elif THE_ISA == SPARC_ISA
-    #include "cpu/o3/sparc/impl.hh"
-#else
-    #error "ISA-specific header files O3CPU not defined ISA"
-#endif
+#include "cpu/o3/impl.hh"
 #include "cpu/o3/dyn_inst.hh"
diff --git a/src/cpu/o3/mips/cpu.cc b/src/cpu/o3/mips/cpu.cc
deleted file mode 100755
index bb78de0a6..000000000
--- a/src/cpu/o3/mips/cpu.cc
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- *          Korey Sewell
- */
-
-#include "cpu/o3/cpu.hh"
-#include "cpu/o3/mips/impl.hh"
-
-// Force instantiation of MipsO3CPU for all the implemntations that are
-// needed.  Consider merging this and mips_dyn_inst.cc, and maybe all
-// classes that depend on a certain impl, into one file (mips_impl.cc?).
-template class FullO3CPU<MipsSimpleImpl>;
diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc
deleted file mode 100644
index 11942e597..000000000
--- a/src/cpu/o3/mips/cpu_builder.cc
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- *          Korey Sewell
- */
-
-#include <string>
-
-#include "config/full_system.hh"
-#include "config/use_checker.hh"
-#include "cpu/o3/cpu.hh"
-#include "cpu/o3/mips/impl.hh"
-#include "params/DerivO3CPU.hh"
-
-class DerivO3CPU : public FullO3CPU<MipsSimpleImpl>
-{
-  public:
-    DerivO3CPU(DerivO3CPUParams *p)
-        : FullO3CPU<MipsSimpleImpl>(p)
-    { }
-};
-
-DerivO3CPU *
-DerivO3CPUParams::create()
-{
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    int actual_num_threads = 1;
-#else
-    // In non-full-system mode, we infer the number of threads from
-    // the workload if it's not explicitly specified.
-    int actual_num_threads =
-        (numThreads >= workload.size()) ? numThreads : workload.size();
-
-    if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
-    }
-#endif
-
-    numThreads = actual_num_threads;
-
-    // Default smtFetchPolicy to "RoundRobin", if necessary.
-    std::string round_robin_policy = "RoundRobin";
-    std::string single_thread = "SingleThread";
-
-    if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
-        smtFetchPolicy = round_robin_policy;
-    else
-        smtFetchPolicy = smtFetchPolicy;
-
-    instShiftAmt = 2;
-
-    return new DerivO3CPU(this);
-}
diff --git a/src/cpu/o3/mips/dyn_inst.cc b/src/cpu/o3/mips/dyn_inst.cc
deleted file mode 100755
index 88205afaf..000000000
--- a/src/cpu/o3/mips/dyn_inst.cc
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- *          Korey Sewell
- */
-
-#include "cpu/o3/dyn_inst_impl.hh"
-#include "cpu/o3/mips/impl.hh"
-
-// Force instantiation of MipsDynInst for all the implementations that
-// are needed.
-template class BaseO3DynInst<MipsSimpleImpl>;
diff --git a/src/cpu/o3/mips/impl.hh b/src/cpu/o3/mips/impl.hh
deleted file mode 100644
index 78afd1387..000000000
--- a/src/cpu/o3/mips/impl.hh
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- *          Korey Sewell
- */
-
-#ifndef __CPU_O3_MIPS_IMPL_HH__
-#define __CPU_O3_MIPS_IMPL_HH__
-
-#include "arch/mips/isa_traits.hh"
-
-#include "cpu/o3/cpu_policy.hh"
-
-// Forward declarations.
-template <class Impl>
-class BaseO3DynInst;
-
-template <class Impl>
-class FullO3CPU;
-
-/** Implementation specific struct that defines several key types to the
- *  CPU, the stages within the CPU, the time buffers, and the DynInst.
- *  The struct defines the ISA, the CPU policy, the specific DynInst, the
- *  specific O3CPU, and all of the structs from the time buffers to do
- *  communication.
- *  This is one of the key things that must be defined for each hardware
- *  specific CPU implementation.
- */
-struct MipsSimpleImpl
-{
-    /** The type of MachInst. */
-    typedef TheISA::MachInst MachInst;
-
-    /** The CPU policy to be used, which defines all of the CPU stages. */
-    typedef SimpleCPUPolicy<MipsSimpleImpl> CPUPol;
-
-    /** The DynInst type to be used. */
-    typedef BaseO3DynInst<MipsSimpleImpl> DynInst;
-
-    /** The refcounted DynInst pointer to be used.  In most cases this is
-     *  what should be used, and not DynInst *.
-     */
-    typedef RefCountingPtr<DynInst> DynInstPtr;
-
-    /** The O3CPU type to be used. */
-    typedef FullO3CPU<MipsSimpleImpl> O3CPU;
-
-    /** Same typedef, but for CPUType.  BaseDynInst may not always use
-     * an O3 CPU, so it's clearer to call it CPUType instead in that
-     * case.
-     */
-    typedef O3CPU CPUType;
-
-    enum {
-      MaxWidth = 8,
-      MaxThreads = 4
-    };
-};
-
-/** The O3Impl to be used. */
-typedef MipsSimpleImpl O3CPUImpl;
-
-#endif // __CPU_O3_MIPS_IMPL_HH__
diff --git a/src/cpu/o3/mips/thread_context.cc b/src/cpu/o3/mips/thread_context.cc
deleted file mode 100755
index 0061a2a63..000000000
--- a/src/cpu/o3/mips/thread_context.cc
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- *          Korey Sewell
- */
-
-#include "cpu/o3/thread_context.hh"
-#include "cpu/o3/thread_context_impl.hh"
-
-template class O3ThreadContext<MipsSimpleImpl>;
-
diff --git a/src/cpu/o3/sparc/cpu.cc b/src/cpu/o3/sparc/cpu.cc
deleted file mode 100644
index 738ff0108..000000000
--- a/src/cpu/o3/sparc/cpu.cc
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "cpu/o3/cpu.hh"
-#include "cpu/o3/sparc/impl.hh"
-
-// Force instantiation of SparcO3CPU for all the implementations that are
-// needed.  Consider merging this and sparc_dyn_inst.cc, and maybe all
-// classes that depend on a certain impl, into one file (sparc_impl.cc?).
-template class FullO3CPU<SparcSimpleImpl>;
diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc
deleted file mode 100644
index c19b4871f..000000000
--- a/src/cpu/o3/sparc/cpu_builder.cc
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include <string>
-
-#include "config/full_system.hh"
-#include "config/use_checker.hh"
-#include "cpu/o3/cpu.hh"
-#include "cpu/o3/sparc/impl.hh"
-#include "params/DerivO3CPU.hh"
-
-class DerivO3CPU : public FullO3CPU<SparcSimpleImpl>
-{
-  public:
-    DerivO3CPU(DerivO3CPUParams *p)
-        : FullO3CPU<SparcSimpleImpl>(p)
-    { }
-};
-
-DerivO3CPU *
-DerivO3CPUParams::create()
-{
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    int actual_num_threads = 1;
-#else
-    // In non-full-system mode, we infer the number of threads from
-    // the workload if it's not explicitly specified.
-    int actual_num_threads =
-        (numThreads >= workload.size()) ? numThreads : workload.size();
-
-    if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
-    }
-#endif
-
-    numThreads = actual_num_threads;
-
-    // Default smtFetchPolicy to "RoundRobin", if necessary.
-    std::string round_robin_policy = "RoundRobin";
-    std::string single_thread = "SingleThread";
-
-    if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
-        smtFetchPolicy = round_robin_policy;
-    else
-        smtFetchPolicy = smtFetchPolicy;
-
-    instShiftAmt = 2;
-
-    return new DerivO3CPU(this);
-}
diff --git a/src/cpu/o3/sparc/thread_context.cc b/src/cpu/o3/sparc/thread_context.cc
deleted file mode 100755
index d85aff502..000000000
--- a/src/cpu/o3/sparc/thread_context.cc
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "cpu/o3/thread_context.hh"
-#include "cpu/o3/thread_context_impl.hh"
-
-template class O3ThreadContext<SparcSimpleImpl>;
-
diff --git a/src/cpu/o3/alpha/thread_context.cc b/src/cpu/o3/thread_context.cc
index 4a02715bc..0d8c67643 100755
--- a/src/cpu/o3/alpha/thread_context.cc
+++ b/src/cpu/o3/thread_context.cc
@@ -26,11 +26,11 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
- *          Korey Sewell
  */
 
 #include "cpu/o3/thread_context.hh"
 #include "cpu/o3/thread_context_impl.hh"
+#include "cpu/o3/impl.hh"
 
-template class O3ThreadContext<AlphaSimpleImpl>;
+template class O3ThreadContext<O3CPUImpl>;
 
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 2c3c3dbc2..8a1b3e749 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -42,7 +42,6 @@
 #include "base/misc.hh"
 #include "base/refcnt.hh"
 #include "cpu/op_class.hh"
-#include "cpu/o3/dyn_inst_decl.hh"
 #include "sim/faults.hh"
 #include "sim/host.hh"
 
@@ -54,6 +53,10 @@ class ThreadContext;
 class DynInst;
 class Packet;
 
+class O3CPUImpl;
+template <class Impl> class BaseO3DynInst;
+typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
+
 template <class Impl>
 class OzoneDynInst;