mem: restructure Packet cmd initialization a bit more

Refactor the way that specific MemCmd values are generated for packets.
The new approach is a little more elegant in that we assign the right
value up front, and it's also more amenable to non-heap-allocated
Packet objects.

Also replaced the code in the Minor model that was still doing it the
ad-hoc way.

This is basically a refinement of http://repo.gem5.org/gem5/rev/711eb0e64249.

4 files changed, 15 insertions, 19 deletions

diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index f8fa3b0d3..78b803501 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -811,10 +811,17 @@ CacheUnit::finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req)
 void
 CacheUnit::buildDataPacket(CacheRequest *cache_req)
 {
-    cache_req->dataPkt = new CacheReqPacket(cache_req,
-                                            cache_req->pktCmd,
+    MemCmd cmd;
+
+    if (cache_req->pktCmd == MemCmd::ReadReq) {
+        cmd = Packet::makeReadCmd(cache_req->memReq);
+    } else {
+        assert(cache_req->pktCmd == MemCmd::WriteReq);
+        cmd = Packet::makeWriteCmd(cache_req->memReq);
+    }
+
+    cache_req->dataPkt = new CacheReqPacket(cache_req, cmd,
                                             cache_req->instIdx);
-    cache_req->dataPkt->refineCommand(); // handle LL/SC, etc.
 
     DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x\n",
             cache_req->getSlot(),
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 65f18eedb..11eb9ddad 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -230,7 +230,7 @@ class CacheRequest : public ResourceRequest
     bool isMemAccPending() { return memAccPending; }
 
     //Make this data private/protected!
-    MemCmd::Command pktCmd;
+    MemCmd pktCmd;
     RequestPtr memReq;
     PacketDataPtr reqData;
     CacheReqPacket *dataPkt;
@@ -252,7 +252,7 @@ class CacheReqPacket : public Packet
 {
   public:
     CacheReqPacket(CacheRequest *_req,
-                   Command _cmd, int _idx = 0)
+                   MemCmd _cmd, int _idx = 0)
         : Packet(&(*_req->memReq), _cmd), cacheReq(_req),
           instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
     {
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index 06b6c5165..ff609deac 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1545,18 +1545,8 @@ PacketPtr
 makePacketForRequest(Request &request, bool isLoad,
     Packet::SenderState *sender_state, PacketDataPtr data)
 {
-    MemCmd command;
-
-    /* Make a ret with the right command type to match the request */
-    if (request.isLLSC()) {
-        command = (isLoad ? MemCmd::LoadLockedReq : MemCmd::StoreCondReq);
-    } else if (request.isSwap()) {
-        command = MemCmd::SwapReq;
-    } else {
-        command = (isLoad ? MemCmd::ReadReq : MemCmd::WriteReq);
-    }
-
-    PacketPtr ret = new Packet(&request, command);
+    PacketPtr ret = isLoad ? Packet::createRead(&request)
+                           : Packet::createWrite(&request);
 
     if (sender_state)
         ret->pushSenderState(sender_state);
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b564521ba..007621feb 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -341,8 +341,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
 
         // Now do the access.
         if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
-            Packet pkt(req, MemCmd::ReadReq);
-            pkt.refineCommand();
+            Packet pkt(req, Packet::makeReadCmd(req));
             pkt.dataStatic(data);
 
             if (req->isMmappedIpr())