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authorNilay Vaish <nilay@cs.wisc.edu>2015-04-29 22:35:22 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-04-29 22:35:22 -0500
commit0dbd696aaef47205c1430b53841423c7d25455ed (patch)
treeeada915ea9c506520042b57a1d011ec3fe18a149 /src/cpu
parentee06fed656d404c19c68c838df1dc8dbba37ec80 (diff)
downloadgem5-0dbd696aaef47205c1430b53841423c7d25455ed.tar.xz
cpu: o3: single cycle default div microop latency on x86
This patch sets the default latency of the division microop to a single cycle on x86. This is because the division instructions DIV and IDIV have been implemented as loops of div microops, where each microop computes a single bit of the quotient.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/FuncUnitConfig.py10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index 34c56163d..0f5efb776 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -39,6 +39,7 @@
# Authors: Kevin Lim
from m5.SimObject import SimObject
+from m5.defines import buildEnv
from m5.params import *
from FuncUnit import *
@@ -49,6 +50,15 @@ class IntALU(FUDesc):
class IntMultDiv(FUDesc):
opList = [ OpDesc(opClass='IntMult', opLat=3),
OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
+
+ # DIV and IDIV instructions in x86 are implemented using a loop which
+ # issues division microops. The latency of these microops should really be
+ # one (or a small number) cycle each since each of these computes one bit
+ # of the quotient.
+ if buildEnv['TARGET_ISA'] in ('x86'):
+ opList[1].opLat=1
+ opList[1].issueLat=1
+
count=2
class FP_ALU(FUDesc):