Traceflags: Add SCons function to created a traceflag instead of having one file with them all.

--HG--
extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6

5 files changed, 64 insertions, 7 deletions

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index b686c0d95..6b43c6c16 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -136,6 +136,7 @@ if env['TARGET_ISA'] == 'x86':
 
 if env['USE_CHECKER']:
     Source('checker/cpu.cc')
+    TraceFlag('Checker')
     checker_supports = False
     for i in CheckerSupportedCPUList:
         if i in env['CPU_MODELS']:
@@ -146,3 +147,26 @@ if env['USE_CHECKER']:
             print i,
         print ", please set USE_CHECKER=False or use one of those CPU models"
         Exit(1)
+
+TraceFlag('Activity')
+TraceFlag('Commit')
+TraceFlag('Decode')
+TraceFlag('DynInst')
+TraceFlag('ExecEnable')
+TraceFlag('ExecCPSeq')
+TraceFlag('ExecEffAddr')
+TraceFlag('ExecFetchSeq')
+TraceFlag('ExecOpClass')
+TraceFlag('ExecRegDelta')
+TraceFlag('ExecResult')
+TraceFlag('ExecSpeculative')
+TraceFlag('ExecSymbol')
+TraceFlag('ExecThread')
+TraceFlag('ExecTicks')
+TraceFlag('Fetch')
+TraceFlag('IntrControl')
+TraceFlag('PCEvent')
+TraceFlag('Quiesce')
+
+CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
+    'ExecEffAddr', 'ExecResult', 'ExecSymbol' ])
diff --git a/src/cpu/memtest/SConscript b/src/cpu/memtest/SConscript
index 1f6621a4c..7832632e4 100644
--- a/src/cpu/memtest/SConscript
+++ b/src/cpu/memtest/SConscript
@@ -34,3 +34,5 @@ if 'O3CPU' in env['CPU_MODELS']:
     SimObject('MemTest.py')
 
     Source('memtest.cc')
+
+    TraceFlag('MemTest')
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index ad61ad228..2de106d8b 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -32,6 +32,16 @@ import sys
 
 Import('*')
 
+if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
+    Source('2bit_local_pred.cc')
+    Source('btb.cc')
+    Source('ras.cc')
+    Source('tournament_pred.cc')
+
+    TraceFlag('CommitRate')
+    TraceFlag('IEW')
+    TraceFlag('IQ')
+
 if 'O3CPU' in env['CPU_MODELS']:
     SimObject('FUPool.py')
     SimObject('FuncUnitConfig.py')
@@ -56,6 +66,21 @@ if 'O3CPU' in env['CPU_MODELS']:
     Source('scoreboard.cc')
     Source('store_set.cc')
 
+    TraceFlag('FreeList')
+    TraceFlag('LSQ')
+    TraceFlag('LSQUnit')
+    TraceFlag('MemDepUnit')
+    TraceFlag('O3CPU')
+    TraceFlag('ROB')
+    TraceFlag('Rename')
+    TraceFlag('Scoreboard')
+    TraceFlag('StoreSet')
+    TraceFlag('Writeback')
+
+    CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
+        'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
+        'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
+
     if env['TARGET_ISA'] == 'alpha':
         Source('alpha/cpu.cc')
         Source('alpha/cpu_builder.cc')
@@ -77,10 +102,3 @@ if 'O3CPU' in env['CPU_MODELS']:
     if env['USE_CHECKER']:
         SimObject('O3Checker.py')
         Source('checker_builder.cc')
-
-if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
-    Source('2bit_local_pred.cc')
-    Source('btb.cc')
-    Source('ras.cc')
-    Source('tournament_pred.cc')
-
diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript
index cb2006456..0ca1a0d07 100644
--- a/src/cpu/ozone/SConscript
+++ b/src/cpu/ozone/SConscript
@@ -44,6 +44,15 @@ if 'OzoneCPU' in env['CPU_MODELS']:
     Source('lw_back_end.cc')
     Source('lw_lsq.cc')
     Source('rename_table.cc')
+
+    TraceFlag('BE')
+    TraceFlag('FE')
+    TraceFlag('IBE')
+    TraceFlag('OzoneCPU')
+    TraceFlag('OzoneLSQ')
+
+    CompoundFlag('OzoneCPUAll', [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU' ])
+
     if env['USE_CHECKER']:
         SimObject('OzoneChecker.py')
         Source('checker_builder.cc')
diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript
index ccccab2b5..c090a938c 100644
--- a/src/cpu/simple/SConscript
+++ b/src/cpu/simple/SConscript
@@ -41,5 +41,9 @@ if 'TimingSimpleCPU' in env['CPU_MODELS']:
     SimObject('TimingSimpleCPU.py')
     Source('timing.cc')
 
+if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
+       'TimingSimpleCPU' in env['CPU_MODELS']:
+    TraceFlag('SimpleCPU')
+
 if need_simple_base:
     Source('base.cc')