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authorGabe Black <gblack@eecs.umich.edu>2006-12-28 14:35:31 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-12-28 14:35:31 -0500
commita0e8aa6737f534a8e51d866728dd6dc59bef263d (patch)
tree8045f52fed7e4ce126ad9861b4595ebc9ba2dd86 /src/cpu
parent3f2b25d99725a8eafd495021a382b7a6ac90720e (diff)
downloadgem5-a0e8aa6737f534a8e51d866728dd6dc59bef263d.tar.xz
Fixes to get non-delay slot ISAs (Alpha) working again, and pulling some debug output out of ifdefs.
--HG-- extra : convert_revision : 29d0969e2d3e809aac32262ba20907e6e4ef1a42
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/iew_impl.hh24
1 files changed, 14 insertions, 10 deletions
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 787d8a26c..63b0d45f8 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -480,8 +480,8 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
toCommit->mispredPC[tid] = inst->readPC();
toCommit->branchMispredict[tid] = true;
-#if ISA_HAS_DELAY_SLOT
int instSize = sizeof(TheISA::MachInst);
+#if ISA_HAS_DELAY_SLOT
bool branch_taken =
!(inst->readNextPC() + instSize == inst->readNextNPC() &&
(inst->readNextPC() == inst->readPC() + instSize ||
@@ -502,12 +502,15 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
if (squashDelaySlot) {
toCommit->nextPC[tid] = inst->readNextPC();
toCommit->nextNPC[tid] = inst->readNextNPC();
- } else
+ } else {
toCommit->nextPC[tid] = inst->readNextNPC();
+ toCommit->nextNPC[tid] = inst->readNextNPC() + instSize;
+ }
#else
toCommit->branchTaken[tid] = inst->readNextPC() !=
(inst->readPC() + sizeof(TheISA::MachInst));
toCommit->nextPC[tid] = inst->readNextPC();
+ toCommit->nextNPC[tid] = inst->readNextPC() + instSize;
#endif
toCommit->includeSquashInst[tid] = false;
@@ -527,6 +530,8 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
toCommit->nextPC[tid] = inst->readNextPC();
#if ISA_HAS_DELAY_SLOT
toCommit->nextNPC[tid] = inst->readNextNPC();
+#else
+ toCommit->nextNPC[tid] = inst->readNextPC() + sizeof(TheISA::MachInst);
#endif
toCommit->branchMispredict[tid] = false;
@@ -547,6 +552,8 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
toCommit->nextPC[tid] = inst->readPC();
#if ISA_HAS_DELAY_SLOT
toCommit->nextNPC[tid] = inst->readNextPC();
+#else
+ toCommit->nextNPC[tid] = inst->readPC() + sizeof(TheISA::MachInst);
#endif
toCommit->branchMispredict[tid] = false;
@@ -1355,14 +1362,11 @@ DefaultIEW<Impl>::executeInsts()
fetchRedirect[tid] = true;
DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
- DPRINTF(IEW, "Predicted target was %#x.\n", inst->predPC);
-#if ISA_HAS_DELAY_SLOT
- DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
- inst->nextNPC);
-#else
- DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
- inst->nextPC);
-#endif
+ DPRINTF(IEW, "Predicted target was %#x, %#x.\n",
+ inst->readPredPC(), inst->readPredNPC());
+ DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
+ " NPC: %#x.\n", inst->readNextPC(),
+ inst->readNextNPC());
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);