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| author | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2010-02-20 20:11:58 +0000 |
|---|---|---|
| committer | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2010-02-20 20:11:58 +0000 |
| commit | a5feaa6a69c28f2ab12e28d47fd4bd62359b07c7 (patch) | |
| tree | 42c742dc4e3a666d529251594a70b7ee47421990 /src/cpu | |
| parent | 29e8bcead5700f638c4848d9b5710d0ebf18d64b (diff) | |
| download | gem5-a5feaa6a69c28f2ab12e28d47fd4bd62359b07c7.tar.xz | |
BaseDynInst: Preserve the faults returned from read and write.
When implementing timing address translations instead of atomic, I
forgot to preserve the faults that are returned from the read and
write calls. This patch reinstates them.
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 65578379b..a9ba12958 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -887,7 +887,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) if (fault == NoFault) { effAddr = req->getVaddr(); effAddrValid = true; - cpu->read(req, sreqLow, sreqHigh, data, lqIdx); + fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); } else { // Return a fixed value to keep simulation deterministic even @@ -933,7 +933,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) if (fault == NoFault) { effAddr = req->getVaddr(); effAddrValid = true; - cpu->write(req, sreqLow, sreqHigh, data, sqIdx); + fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); } return fault; |