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authorGabe Black <gblack@eecs.umich.edu>2007-01-29 10:48:20 -0500
committerGabe Black <gblack@eecs.umich.edu>2007-01-29 10:48:20 -0500
commite176c7d1ff5b4470a7602b124eebe1db9e63660d (patch)
tree856dccd2f5f67287a79b66a4d87ae80a6ecbc8f0 /src/cpu
parent105c3367438c3a1dd40be808cdba848eb813b54d (diff)
downloadgem5-e176c7d1ff5b4470a7602b124eebe1db9e63660d.tar.xz
A minor hack to get branch prediction to behave like before on Alpha.
--HG-- extra : convert_revision : 1eaabd13c72aa42c512a04d162a87491818bc621
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/fetch_impl.hh4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 90d3868a5..b80fc72e1 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1150,6 +1150,10 @@ DefaultFetch<Impl>::fetch(bool &status_change)
instruction->staticInst,
instruction->readPC());
+ ///FIXME This needs to be more robust in dealing with delay slots
+#if !ISA_HAS_DELAY_SLOT
+ predicted_branch |=
+#endif
lookupAndUpdateNextPC(instruction, next_PC, next_NPC);
predicted_branch |= (next_PC != fetch_NPC);