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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-01-07 13:05:45 -0500
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-01-07 13:05:45 -0500
commitfb52ea9220f307de18da6565a2cbbaf67ba2b7a7 (patch)
tree879d47a6ccb3333c7c9e38d508aa54f55b70e940 /src/cpu
parent0d59549cd9db2263b1cc1b90e8abd05229eaab5b (diff)
downloadgem5-fb52ea9220f307de18da6565a2cbbaf67ba2b7a7.tar.xz
arm: Invalidate cached TLB configuration in drainResume
Currently, we invalidate the cached miscregs in TLB::unserialize(). The intended use of the drainResume() method is to invalidate cached state and prepare the system to resume after a CPU handover or (un)serialization. This patch moves the TLB miscregs invalidation code to the drainResume() method to avoid surprising behavior.
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