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authorLisa Hsu <hsul@eecs.umich.edu>2007-01-19 21:34:21 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2007-01-19 21:34:21 -0500
commit01c959aeaf7f4c6e15bae9d8de227b6d2cbb7ae1 (patch)
tree158f99a529eccb9c4835a2f544cc4ce59d482ec8 /src/cpu
parentf1aeaf7ceb44ea6ef7032048a68c74ecedc7685b (diff)
parentae0d8d16818e49a16a3c2fa0553acf60514934e6 (diff)
downloadgem5-01c959aeaf7f4c6e15bae9d8de227b6d2cbb7ae1.tar.xz
Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5 --HG-- extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/exetrace.cc54
-rw-r--r--src/cpu/simple/atomic.cc2
-rw-r--r--src/cpu/simple/base.cc1
-rw-r--r--src/cpu/static_inst.hh2
4 files changed, 43 insertions, 16 deletions
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 6e0bf6d33..87075c1ec 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -59,6 +59,7 @@ using namespace TheISA;
#if THE_ISA == SPARC_ISA && FULL_SYSTEM
static int diffcount = 0;
+static bool wasMicro = false;
#endif
namespace Trace {
@@ -124,6 +125,7 @@ inline void printLevelHeader(ostream & os, int level)
void
Trace::InstRecord::dump(ostream &outs)
{
+ DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst);
if (flags[PRINT_REG_DELTA])
{
#if THE_ISA == SPARC_ISA
@@ -315,6 +317,24 @@ Trace::InstRecord::dump(ostream &outs)
bool diffTlb = false;
Addr m5Pc, lgnPc;
+ // We took a trap on a micro-op...
+ if (wasMicro && !staticInst->isMicroOp())
+ {
+ // let's skip comparing this cycle
+ while (!compared)
+ if (shared_data->flags == OWN_M5) {
+ shared_data->flags = OWN_LEGION;
+ compared = true;
+ }
+ compared = false;
+ wasMicro = false;
+ }
+
+ if (staticInst->isLastMicroOp())
+ wasMicro = false;
+ else if (staticInst->isMicroOp())
+ wasMicro = true;
+
if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
while (!compared) {
@@ -587,24 +607,28 @@ Trace::InstRecord::dump(ostream &outs)
<< endl;*/
}
}
- printColumnLabels(outs);
- char label[8];
- for (int x = 0; x < 64; x++) {
- if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) ||
- thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) {
- sprintf(label, "I-TLB:%02d", x);
- printRegPair(outs, label, thread->getITBPtr()->TteRead(x), shared_data->itb[x]);
+ if (diffTlb) {
+ printColumnLabels(outs);
+ char label[8];
+ for (int x = 0; x < 64; x++) {
+ if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) ||
+ thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) {
+ sprintf(label, "I-TLB:%02d", x);
+ printRegPair(outs, label, thread->getITBPtr()->TteRead(x),
+ shared_data->itb[x]);
+ }
}
- }
- for (int x = 0; x < 64; x++) {
- if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) ||
- thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) {
- sprintf(label, "D-TLB:%02d", x);
- printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), shared_data->dtb[x]);
+ for (int x = 0; x < 64; x++) {
+ if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) ||
+ thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) {
+ sprintf(label, "D-TLB:%02d", x);
+ printRegPair(outs, label, thread->getDTBPtr()->TteRead(x),
+ shared_data->dtb[x]);
+ }
}
+ thread->getITBPtr()->dumpAll();
+ thread->getDTBPtr()->dumpAll();
}
- thread->getITBPtr()->dumpAll();
- thread->getDTBPtr()->dumpAll();
diffcount++;
if (diffcount > 2)
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 8db864153..3b3536e44 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -497,7 +497,7 @@ AtomicSimpleCPU::tick()
// @todo remove me after debugging with legion done
if (curStaticInst && (!curStaticInst->isMicroOp() ||
- curStaticInst->isLastMicroOp()))
+ curStaticInst->isFirstMicroOp()))
instCnt++;
if (simulate_stalls) {
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 4e5754bbb..ddccc5a9b 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -437,6 +437,7 @@ void
BaseSimpleCPU::advancePC(Fault fault)
{
if (fault != NoFault) {
+ curMacroStaticInst = StaticInst::nullStaticInstPtr;
fault->invoke(tc);
} else {
//If we're at the last micro op for this instruction
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 523cfae40..5928eea76 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -146,6 +146,7 @@ class StaticInstBase : public RefCounted
IsMicroOp, ///< Is a microop
IsDelayedCommit, ///< This microop doesn't commit right away
IsLastMicroOp, ///< This microop ends a microop sequence
+ IsFirstMicroOp, ///< This microop begins a microop sequence
//This flag doesn't do anything yet
IsMicroBranch, ///< This microop branches within the microcode for a macroop
@@ -244,6 +245,7 @@ class StaticInstBase : public RefCounted
bool isMicroOp() const { return flags[IsMicroOp]; }
bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
+ bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; }
//This flag doesn't do anything yet
bool isMicroBranch() const { return flags[IsMicroBranch]; }
//@}