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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:29:09 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:29:09 -0700 |
| commit | 24bfda0fdf0d1f80726d8590dcd6a84d70134a53 (patch) | |
| tree | 6fc321f0223497ca1a9e635fa5d511beba5c37fe /src/cpu | |
| parent | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (diff) | |
| download | gem5-24bfda0fdf0d1f80726d8590dcd6a84d70134a53.tar.xz | |
Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.
--HG--
extra : convert_revision : 4446d9544d58bdadbd24d8322bb63016a32aa2b8
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 8 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 14 |
2 files changed, 20 insertions, 2 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 8a05d800e..234803be5 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -618,13 +618,17 @@ AtomicSimpleCPU::tick() preExecute(); - if(curStaticInst) - { + if (curStaticInst) { fault = curStaticInst->execute(this, traceData); // keep an instruction count if (fault == NoFault) countInst(); + else if (traceData) { + // If there was a fault, we should trace this instruction. + delete traceData; + traceData = NULL; + } postExecute(); } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 046b2fe3b..1e1f43f7d 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -544,6 +544,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) // keep an instruction count if (fault == NoFault) countInst(); + } else if (traceData) { + // If there was a fault, we shouldn't trace this instruction. + delete traceData; + traceData = NULL; } postExecute(); @@ -556,6 +560,11 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) // keep an instruction count if (fault == NoFault) countInst(); + else if (traceData) { + // If there was a fault, we shouldn't trace this instruction. + delete traceData; + traceData = NULL; + } postExecute(); advanceInst(fault); @@ -628,6 +637,11 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) // keep an instruction count if (fault == NoFault) countInst(); + else if (traceData) { + // If there was a fault, we shouldn't trace this instruction. + delete traceData; + traceData = NULL; + } if (pkt->isRead() && pkt->isLocked()) { TheISA::handleLockedRead(thread, pkt->req); |