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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 11:08:00 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 11:08:00 -0700 |
| commit | 42ebebf99a7d6ce2358b152f643b52c7946f9202 (patch) | |
| tree | 2255b51553c45c650a94950b1654cdec917ff339 /src/cpu | |
| parent | d9f9c967fbe651e09d444e460a9b1c5a450b1cd2 (diff) | |
| download | gem5-42ebebf99a7d6ce2358b152f643b52c7946f9202.tar.xz | |
X86: Make the local APIC accessible through the memory system directly, and make the timer work.
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/BaseCPU.py | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index c2385f6d0..78b9ae944 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -97,8 +97,9 @@ class BaseCPU(MemObject): dtb = Param.X86DTB(X86DTB(), "Data TLB") itb = Param.X86ITB(X86ITB(), "Instruction TLB") if build_env['FULL_SYSTEM']: - interrupts = Param.X86LocalApic( - X86LocalApic(), "Interrupt Controller") + _localApic = X86LocalApic(pio_addr=0xa000000000000000) + interrupts = \ + Param.X86LocalApic(_localApic, "Interrupt Controller") elif build_env['TARGET_ISA'] == 'mips': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.MipsDTB(MipsDTB(), "Data TLB") @@ -141,7 +142,9 @@ class BaseCPU(MemObject): _mem_ports = [] if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: - _mem_ports = ["itb.walker.port", "dtb.walker.port"] + _mem_ports = ["itb.walker.port", + "dtb.walker.port", + "interrupts.pio"] def connectMemPorts(self, bus): for p in self._mem_ports: |