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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:20 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:20 -0500 |
| commit | 53ab306acc725670138d6f65ae2dbef241ac49a3 (patch) | |
| tree | a8be451263e5166c04c2fc60dfd3bbba200e71a6 /src/cpu | |
| parent | 4c7a7796ade354a41fac9b4c14d4715cbe9e78c4 (diff) | |
| download | gem5-53ab306acc725670138d6f65ae2dbef241ac49a3.tar.xz | |
ARM: Fix subtle bug in LDM.
If the instruction faults mid-op the base register shouldn't be written back.
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/static_inst.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 933496864..d07b322df 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -267,6 +267,7 @@ class StaticInstBase : public RefCounted void setLastMicroop() { flags[IsLastMicroop] = true; } void setDelayedCommit() { flags[IsDelayedCommit] = true; } + void setFlag(Flags f) { flags[f] = true; } /// Operation class. Used to select appropriate function unit in issue. OpClass opClass() const { return _opClass; } |