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authorAli Saidi <saidi@eecs.umich.edu>2006-06-26 17:50:48 -0400
committerAli Saidi <saidi@eecs.umich.edu>2006-06-26 17:50:48 -0400
commit60454042aaf1c5b3380536c4a1d2255d8f648d7d (patch)
tree38bc7ccb4dce874e24d9a66d551eed8c7e590367 /src/cpu
parentb1cfe01b5730af7d9f215466ebe108fc96dc0a27 (diff)
downloadgem5-60454042aaf1c5b3380536c4a1d2255d8f648d7d.tar.xz
don't depend on the memory system to return the atomic cpu a multiple of cpu cycles.
--HG-- extra : convert_revision : e5eb36f14c8394381a0269fefd34a178833c8346
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/simple/atomic.cc11
1 files changed, 5 insertions, 6 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 071193f02..ce28ba9c8 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -410,15 +410,14 @@ AtomicSimpleCPU::tick()
postExecute();
if (simulate_stalls) {
- // This calculation assumes that the icache and dcache
- // access latencies are always a multiple of the CPU's
- // cycle time. If not, the next tick event may get
- // scheduled at a non-integer multiple of the CPU
- // cycle time.
Tick icache_stall = icache_latency - cycles(1);
Tick dcache_stall =
dcache_access ? dcache_latency - cycles(1) : 0;
- latency += icache_stall + dcache_stall;
+ Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
+ if (cycles(stall_cycles) < (icache_stall + dcache_stall))
+ latency += cycles(stall_cycles+1);
+ else
+ latency += cycles(stall_cycles);
}
}