Merge zizzer.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 91aacb435c223e8c37f6ba0a458b0dee55edcaf2

5 files changed, 75 insertions, 48 deletions

diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 748f66d37..8b1e60aea 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -42,6 +42,9 @@
 #include "sim/param.hh"
 #include "sim/system.hh"
 
+//XXX This is temporary
+#include "arch/isa_specific.hh"
+
 using namespace std;
 using namespace TheISA;
 
@@ -56,43 +59,67 @@ Trace::InstRecord::dump(ostream &outs)
 {
     if (flags[PRINT_REG_DELTA])
     {
-        outs << "PC = 0x" << setbase(16)
-                        << setfill('0')
-                        << setw(16) << PC << endl;
-        outs << setbase(10)
-             << setfill(' ')
-             << setw(0);
-        /*
-        int numSources = staticInst->numSrcRegs();
-        int numDests = staticInst->numDestRegs();
-        outs << "Sources:";
-        for(int x = 0; x < numSources; x++)
+#if THE_ISA == SPARC_ISA
+        static uint64_t regs[32] = {
+            0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, 0};
+        static uint64_t ccr = 0;
+        static uint64_t y = 0;
+        static uint64_t floats[32];
+        uint64_t newVal;
+        static const char * prefixes[4] = {"G", "O", "L", "I"};
+
+        char buf[256];
+        sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
+        outs << buf;
+        sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
+        outs << buf;
+        newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
+        if(newVal != ccr)
         {
-            int sourceNum = staticInst->srcRegIdx(x);
-            if(sourceNum < FP_Base_DepTag)
-                outs << " " << getIntRegName(sourceNum);
-            else if(sourceNum < Ctrl_Base_DepTag)
-                outs << " " << getFloatRegName(sourceNum - FP_Base_DepTag);
-            else
-                outs << " " << getMiscRegName(sourceNum - Ctrl_Base_DepTag);
+            sprintf(buf, " CCR = 0x%016llx", newVal);
+            outs << buf;
+            ccr = newVal;
         }
-        outs << endl;
-        outs << "Destinations:";
-        for(int x = 0; x < numDests; x++)
+        newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
+        if(newVal != y)
         {
-            int destNum = staticInst->destRegIdx(x);
-            if(destNum < FP_Base_DepTag)
-                outs << " " << getIntRegName(destNum);
-            else if(destNum < Ctrl_Base_DepTag)
-                outs << " " << getFloatRegName(destNum - FP_Base_DepTag);
-            else
-                outs << " " << getMiscRegName(destNum - Ctrl_Base_DepTag);
+            sprintf(buf, " Y = 0x%016llx", newVal);
+            outs << buf;
+            y = newVal;
+        }
+        for(int y = 0; y < 4; y++)
+        {
+            for(int x = 0; x < 8; x++)
+            {
+                int index = x + 8 * y;
+                newVal = thread->readIntReg(index);
+                if(regs[index] != newVal)
+                {
+                    sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
+                    outs << buf;
+                    regs[index] = newVal;
+                }
+            }
+        }
+        for(int y = 0; y < 32; y++)
+        {
+            newVal = thread->readFloatRegBits(2 * y, 64);
+            if(floats[y] != newVal)
+            {
+                sprintf(buf, " F%d = 0x%016llx", y, newVal);
+                outs << buf;
+                floats[y] = newVal;
+            }
         }
-        outs << endl;*/
+        outs << endl;
+#endif
     }
     else if (flags[INTEL_FORMAT]) {
 #if FULL_SYSTEM
-        bool is_trace_system = (cpu->system->name() == trace_system);
+        bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
 #else
         bool is_trace_system = true;
 #endif
@@ -112,13 +139,13 @@ Trace::InstRecord::dump(ostream &outs)
         if (flags[PRINT_CYCLE])
             ccprintf(outs, "%7d: ", cycle);
 
-        outs << cpu->name() << " ";
+        outs << thread->getCpuPtr()->name() << " ";
 
         if (flags[TRACE_MISSPEC])
             outs << (misspeculating ? "-" : "+") << " ";
 
         if (flags[PRINT_THREAD_NUM])
-            outs << "T" << thread << " : ";
+            outs << "T" << thread->getThreadNum() << " : ";
 
 
         std::string sym_str;
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index 8cc98b777..02ea162f0 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -41,7 +41,7 @@
 #include "cpu/thread_context.hh"
 #include "cpu/static_inst.hh"
 
-class BaseCPU;
+class ThreadContext;
 
 
 namespace Trace {
@@ -53,13 +53,12 @@ class InstRecord : public Record
 
     // The following fields are initialized by the constructor and
     // thus guaranteed to be valid.
-    BaseCPU *cpu;
+    ThreadContext *thread;
     // need to make this ref-counted so it doesn't go away before we
     // dump the record
     StaticInstPtr staticInst;
     Addr PC;
     bool misspeculating;
-    unsigned thread;
 
     // The remaining fields are only valid for particular instruction
     // types (e.g, addresses for memory ops) or when particular
@@ -95,11 +94,12 @@ class InstRecord : public Record
     bool regs_valid;
 
   public:
-    InstRecord(Tick _cycle, BaseCPU *_cpu,
+    InstRecord(Tick _cycle, ThreadContext *_thread,
                const StaticInstPtr &_staticInst,
-               Addr _pc, bool spec, int _thread)
-        : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
-          misspeculating(spec), thread(_thread)
+               Addr _pc, bool spec)
+        : Record(_cycle), thread(_thread),
+          staticInst(_staticInst), PC(_pc),
+          misspeculating(spec)
     {
         data_status = DataInvalid;
         addr_valid = false;
@@ -174,14 +174,14 @@ InstRecord::setRegs(const IntRegFile &regs)
 
 inline
 InstRecord *
-getInstRecord(Tick cycle, ThreadContext *tc, BaseCPU *cpu,
+getInstRecord(Tick cycle, ThreadContext *tc,
               const StaticInstPtr staticInst,
-              Addr pc, int thread = 0)
+              Addr pc)
 {
     if (DTRACE(InstExec) &&
         (InstRecord::traceMisspec() || !tc->misspeculating())) {
-        return new InstRecord(cycle, cpu, staticInst, pc,
-                              tc->misspeculating(), thread);
+        return new InstRecord(cycle, tc, staticInst, pc,
+                              tc->misspeculating());
     }
 
     return NULL;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index bf9a73902..1e080181c 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1129,9 +1129,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                     tid, instruction->staticInst->disassemble(fetch_PC));
 
             instruction->traceData =
-                Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
+                Trace::getInstRecord(curTick, cpu->tcBase(tid),
                                      instruction->staticInst,
-                                     instruction->readPC(),tid);
+                                     instruction->readPC());
 
             predicted_branch = lookupAndUpdateNextPC(instruction, next_PC,
                                                      next_NPC);
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index c9c5a869b..1b120460a 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -855,9 +855,9 @@ FrontEnd<Impl>::getInstFromCacheline()
             instruction->staticInst->disassemble(PC));
 
     instruction->traceData =
-        Trace::getInstRecord(curTick, tc, cpu,
+        Trace::getInstRecord(curTick, tc,
                              instruction->staticInst,
-                             instruction->readPC(), 0);
+                             instruction->readPC());
 
     // Increment stat of fetched instructions.
     ++fetchedInsts;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 22a210115..f801b93fa 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -398,7 +398,7 @@ BaseSimpleCPU::preExecute()
     inst = gtoh(inst);
     curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC()));
 
-    traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst,
+    traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
                                      thread->readPC());
 
     DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",