summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorSteve Reinhardt <stever@eecs.umich.edu>2007-02-07 10:53:37 -0800
committerSteve Reinhardt <stever@eecs.umich.edu>2007-02-07 10:53:37 -0800
commit997fc505a8b2ed843f2c87bd2371e6510f731324 (patch)
tree5dd0911a77a2f36e6ee2b9dffc9af68783739134 /src/cpu
parent23d970e6b91158350c1ef694f26d24851e7c34c5 (diff)
downloadgem5-997fc505a8b2ed843f2c87bd2371e6510f731324.tar.xz
Make memory commands dense again to avoid cache stat table explosion.
Created MemCmd class to wrap enum and provide handy methods to check attributes, convert to string/int, etc. --HG-- extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/memtest/memtest.cc10
-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rw-r--r--src/cpu/o3/lsq_unit.hh5
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh3
-rw-r--r--src/cpu/simple/atomic.cc6
-rw-r--r--src/cpu/simple/timing.cc6
6 files changed, 17 insertions, 15 deletions
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 180f41541..8b3e9a11e 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -226,8 +226,8 @@ MemTest::completeRequest(PacketPtr pkt)
assert(removeAddr != outstandingAddrs.end());
outstandingAddrs.erase(removeAddr);
- switch (pkt->cmd) {
- case Packet::ReadResp:
+ switch (pkt->cmd.toInt()) {
+ case MemCmd::ReadResp:
if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
cerr << name() << ": on read of 0x" << hex << req->getPaddr()
@@ -254,7 +254,7 @@ MemTest::completeRequest(PacketPtr pkt)
exitSimLoop("Maximum number of loads reached!");
break;
- case Packet::WriteResp:
+ case MemCmd::WriteResp:
numWritesStat++;
break;
/*
@@ -389,7 +389,7 @@ MemTest::tick()
<< dec << curTick << endl;
}
- PacketPtr pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
MemTestSenderState *state = new MemTestSenderState(result);
pkt->senderState = state;
@@ -429,7 +429,7 @@ MemTest::tick()
<< dec << curTick << endl;
}
*/
- PacketPtr pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
uint8_t *pkt_data = new uint8_t[req->getSize()];
pkt->dataDynamicArray(pkt_data);
memcpy(pkt_data, &data, req->getSize());
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index b80fc72e1..e6a779823 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -602,7 +602,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
// Build packet here.
PacketPtr data_pkt = new Packet(mem_req,
- Packet::ReadReq, Packet::Broadcast);
+ MemCmd::ReadReq, Packet::Broadcast);
data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
cacheDataPC[tid] = block_PC;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 9c7eb7780..2419afe29 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -574,7 +574,8 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
"addr %#x, data %#x\n",
store_idx, req->getVaddr(), data);
- PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
+ Packet::Broadcast);
data_pkt->dataStatic(load_inst->memData);
WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
@@ -638,7 +639,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
// if we the cache is not blocked, do cache access
if (!lsq->cacheBlocked()) {
PacketPtr data_pkt =
- new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
data_pkt->dataStatic(load_inst->memData);
LSQSenderState *state = new LSQSenderState;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index ebd9301f6..3ba22a530 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -613,7 +613,8 @@ LSQUnit<Impl>::writebackStores()
(sizeof(TheISA::IntReg) - req->getSize()) : 0),
req->getSize());
- PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
+ Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 3b3536e44..fa47b0eee 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -138,18 +138,18 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
ifetch_req = new Request();
ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
- ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
+ ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
ifetch_pkt->dataStatic(&inst);
data_read_req = new Request();
data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
- data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
+ data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq,
Packet::Broadcast);
data_read_pkt->dataStatic(&dataReg);
data_write_req = new Request();
data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
- data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
+ data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
Packet::Broadcast);
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index dfffb0b1f..e4748c966 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -286,7 +286,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// Now do the access.
if (fault == NoFault) {
PacketPtr pkt =
- new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
pkt->dataDynamic<T>(new T);
if (!dcachePort.sendTiming(pkt)) {
@@ -365,7 +365,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// Now do the access.
if (fault == NoFault) {
assert(dcache_pkt == NULL);
- dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+ dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
dcache_pkt->allocate();
dcache_pkt->set(data);
@@ -454,7 +454,7 @@ TimingSimpleCPU::fetch()
ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
Fault fault = setupFetchRequest(ifetch_req);
- ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
+ ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
ifetch_pkt->dataStatic(&inst);
if (fault == NoFault) {