python: Move more code into m5.util allow SCons to use that code.

Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.

--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py

11 files changed, 39 insertions, 44 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 4661375ba..75114053e 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -26,36 +26,38 @@
 #
 # Authors: Nathan Binkert
 
-from MemObject import MemObject
+import sys
+
+from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from m5 import build_env
+
 from Bus import Bus
 from InstTracer import InstTracer
 from ExeTracer import ExeTracer
-import sys
+from MemObject import MemObject
 
 default_tracer = ExeTracer()
 
-if build_env['TARGET_ISA'] == 'alpha':
+if buildEnv['TARGET_ISA'] == 'alpha':
     from AlphaTLB import AlphaDTB, AlphaITB
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         from AlphaInterrupts import AlphaInterrupts
-elif build_env['TARGET_ISA'] == 'sparc':
+elif buildEnv['TARGET_ISA'] == 'sparc':
     from SparcTLB import SparcTLB
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         from SparcInterrupts import SparcInterrupts
-elif build_env['TARGET_ISA'] == 'x86':
+elif buildEnv['TARGET_ISA'] == 'x86':
     from X86TLB import X86TLB
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         from X86LocalApic import X86LocalApic
-elif build_env['TARGET_ISA'] == 'mips':
+elif buildEnv['TARGET_ISA'] == 'mips':
     from MipsTLB import MipsTLB
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         from MipsInterrupts import MipsInterrupts
-elif build_env['TARGET_ISA'] == 'arm':
+elif buildEnv['TARGET_ISA'] == 'arm':
     from ArmTLB import ArmTLB
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         from ArmInterrupts import ArmInterrupts
 
 class BaseCPU(MemObject):
@@ -76,47 +78,47 @@ class BaseCPU(MemObject):
     do_statistics_insts = Param.Bool(True,
         "enable statistics pseudo instructions")
 
-    if build_env['FULL_SYSTEM']:
+    if buildEnv['FULL_SYSTEM']:
         profile = Param.Latency('0ns', "trace the kernel stack")
         do_quiesce = Param.Bool(True, "enable quiesce instructions")
     else:
         workload = VectorParam.Process("processes to run")
 
-    if build_env['TARGET_ISA'] == 'sparc':
+    if buildEnv['TARGET_ISA'] == 'sparc':
         dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
         itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
-        if build_env['FULL_SYSTEM']:
+        if buildEnv['FULL_SYSTEM']:
             interrupts = Param.SparcInterrupts(
                 SparcInterrupts(), "Interrupt Controller")
-    elif build_env['TARGET_ISA'] == 'alpha':
+    elif buildEnv['TARGET_ISA'] == 'alpha':
         dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
         itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
-        if build_env['FULL_SYSTEM']:
+        if buildEnv['FULL_SYSTEM']:
             interrupts = Param.AlphaInterrupts(
                 AlphaInterrupts(), "Interrupt Controller")
-    elif build_env['TARGET_ISA'] == 'x86':
+    elif buildEnv['TARGET_ISA'] == 'x86':
         dtb = Param.X86TLB(X86TLB(), "Data TLB")
         itb = Param.X86TLB(X86TLB(), "Instruction TLB")
-        if build_env['FULL_SYSTEM']:
+        if buildEnv['FULL_SYSTEM']:
             _localApic = X86LocalApic(pio_addr=0x2000000000000000)
             interrupts = \
                 Param.X86LocalApic(_localApic, "Interrupt Controller")
-    elif build_env['TARGET_ISA'] == 'mips':
+    elif buildEnv['TARGET_ISA'] == 'mips':
         dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
         itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
-        if build_env['FULL_SYSTEM']:
+        if buildEnv['FULL_SYSTEM']:
             interrupts = Param.MipsInterrupts(
                     MipsInterrupts(), "Interrupt Controller")
-    elif build_env['TARGET_ISA'] == 'arm':
+    elif buildEnv['TARGET_ISA'] == 'arm':
         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
         dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
         itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
-        if build_env['FULL_SYSTEM']:
+        if buildEnv['FULL_SYSTEM']:
             interrupts = Param.ArmInterrupts(
                     ArmInterrupts(), "Interrupt Controller")
     else:
         print "Don't know what TLB to use for ISA %s" % \
-            build_env['TARGET_ISA']
+            buildEnv['TARGET_ISA']
         sys.exit(1)
 
     max_insts_all_threads = Param.Counter(0,
@@ -139,7 +141,7 @@ class BaseCPU(MemObject):
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
     _mem_ports = []
-    if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
+    if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
         _mem_ports = ["itb.walker.port",
                       "dtb.walker.port",
                       "interrupts.pio",
@@ -157,7 +159,7 @@ class BaseCPU(MemObject):
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
         self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
-        if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
+        if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
             self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
@@ -168,7 +170,7 @@ class BaseCPU(MemObject):
         self.l2cache.cpu_side = self.toL2Bus.port
         self._mem_ports = ['l2cache.mem_side']
 
-    if build_env['TARGET_ISA'] == 'mips':
+    if buildEnv['TARGET_ISA'] == 'mips':
         CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
         CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
         CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py
index bff9af62d..132254413 100644
--- a/src/cpu/CheckerCPU.py
+++ b/src/cpu/CheckerCPU.py
@@ -27,7 +27,6 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
 class CheckerCPU(BaseCPU):
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index 9faadc68c..a0b0466a7 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -28,7 +28,6 @@
 
 from m5.params import *
 from m5.proxy import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
 class InOrderCPU(BaseCPU):
diff --git a/src/cpu/memtest/MemTest.py b/src/cpu/memtest/MemTest.py
index 629fd4877..8e1b3a8d0 100644
--- a/src/cpu/memtest/MemTest.py
+++ b/src/cpu/memtest/MemTest.py
@@ -29,7 +29,6 @@
 from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
-from m5 import build_env
 
 class MemTest(MemObject):
     type = 'MemTest'
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 56e537ad2..3f2210e44 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -26,21 +26,21 @@
 #
 # Authors: Kevin Lim
 
+from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 from FUPool import *
 
-if build_env['USE_CHECKER']:
+if buildEnv['USE_CHECKER']:
     from O3Checker import O3Checker
 
 class DerivO3CPU(BaseCPU):
     type = 'DerivO3CPU'
     activity = Param.Unsigned(0, "Initial count")
 
-    if build_env['USE_CHECKER']:
-        if not build_env['FULL_SYSTEM']:
+    if buildEnv['USE_CHECKER']:
+        if not buildEnv['FULL_SYSTEM']:
             checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
                                               exitOnError=False,
                                               updateOnError=True,
diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py
index edc6dc9b6..d0c4ce537 100644
--- a/src/cpu/o3/O3Checker.py
+++ b/src/cpu/o3/O3Checker.py
@@ -27,7 +27,6 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
 class O3Checker(BaseCPU):
diff --git a/src/cpu/ozone/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py
index 37386898d..2c7b8475f 100644
--- a/src/cpu/ozone/OzoneCPU.py
+++ b/src/cpu/ozone/OzoneCPU.py
@@ -26,11 +26,11 @@
 #
 # Authors: Kevin Lim
 
+from m5.defines import buildEnv
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
-if build_env['USE_CHECKER']:
+if buildEnv['USE_CHECKER']:
     from OzoneChecker import OzoneChecker
 
 class DerivOzoneCPU(BaseCPU):
@@ -38,7 +38,7 @@ class DerivOzoneCPU(BaseCPU):
 
     numThreads = Param.Unsigned("number of HW thread contexts")
 
-    if build_env['USE_CHECKER']:
+    if buildEnv['USE_CHECKER']:
         checker = Param.BaseCPU("Checker CPU")
 
     icache_port = Port("Instruction Port")
diff --git a/src/cpu/ozone/OzoneChecker.py b/src/cpu/ozone/OzoneChecker.py
index bfa39ead9..bbe46db18 100644
--- a/src/cpu/ozone/OzoneChecker.py
+++ b/src/cpu/ozone/OzoneChecker.py
@@ -27,7 +27,6 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
 class OzoneChecker(BaseCPU):
diff --git a/src/cpu/ozone/SimpleOzoneCPU.py b/src/cpu/ozone/SimpleOzoneCPU.py
index 93603092b..d4620cd8e 100644
--- a/src/cpu/ozone/SimpleOzoneCPU.py
+++ b/src/cpu/ozone/SimpleOzoneCPU.py
@@ -26,8 +26,8 @@
 #
 # Authors: Kevin Lim
 
+from m5.defines import buildEnv
 from m5.params import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
 class SimpleOzoneCPU(BaseCPU):
@@ -35,7 +35,7 @@ class SimpleOzoneCPU(BaseCPU):
 
     numThreads = Param.Unsigned("number of HW thread contexts")
 
-    if not build_env['FULL_SYSTEM']:
+    if not buildEnv['FULL_SYSTEM']:
         mem = Param.FunctionalMemory(NULL, "memory")
 
     width = Param.Unsigned("Width")
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index b7174bb43..3d72f4098 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -27,7 +27,6 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseSimpleCPU import BaseSimpleCPU
 
 class AtomicSimpleCPU(BaseSimpleCPU):
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index ce6839241..6b83c41aa 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -27,7 +27,6 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5 import build_env
 from BaseSimpleCPU import BaseSimpleCPU
 
 class TimingSimpleCPU(BaseSimpleCPU):