diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-28 14:27:45 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-28 14:27:45 -0500 |
commit | b642ad00eb55678f4ce20fdf127a00a6c0bbdcb8 (patch) | |
tree | 37280a2bade801cc43d66702b537cfa0c51ba91b /src/cpu | |
parent | 9ca6efdb60866b1feada0295b02fdc7ff49eacf2 (diff) | |
download | gem5-b642ad00eb55678f4ce20fdf127a00a6c0bbdcb8.tar.xz |
Implement a stub nnpc for alpha that is read only as npc+4.
--HG--
extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/base_dyn_inst.hh | 15 | ||||
-rw-r--r-- | src/cpu/o3/alpha/thread_context.hh | 3 | ||||
-rw-r--r-- | src/cpu/o3/cpu.cc | 2 | ||||
-rw-r--r-- | src/cpu/ozone/cpu.hh | 12 |
4 files changed, 24 insertions, 8 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 07d53d278..515cd0836 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -209,6 +209,7 @@ class BaseDynInst : public FastAlloc, public RefCounted /** PC of this instruction. */ Addr PC; + protected: /** Next non-speculative PC. It is not filled in at fetch, but rather * once the target of the branch is truly known (either decode or * execute). @@ -227,6 +228,8 @@ class BaseDynInst : public FastAlloc, public RefCounted /** If this is a branch that was predicted taken */ bool predTaken; + public: + /** Count of total number of dynamic instructions. */ static int instcount; @@ -390,7 +393,14 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Returns the next NPC. This could be the speculative next NPC if it is * called prior to the actual branch target being calculated. */ - Addr readNextNPC() { return nextNPC; } + Addr readNextNPC() + { +#if ISA_HAS_DELAY_SLOT + return nextNPC; +#else + return nextPC + sizeof(TheISA::MachInst); +#endif + } /** Set the predicted target of this current instruction. */ void setPredTarg(Addr predicted_PC, Addr predicted_NPC) @@ -419,7 +429,8 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Returns whether the instruction mispredicted. */ bool mispredicted() { - return predPC != nextPC || predNPC != nextNPC; + return readPredPC() != readNextPC() || + readPredNPC() != readNextNPC(); } // diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh index e4a6735c2..6d61501ac 100644 --- a/src/cpu/o3/alpha/thread_context.hh +++ b/src/cpu/o3/alpha/thread_context.hh @@ -45,8 +45,7 @@ class AlphaTC : public O3ThreadContext<Impl> virtual uint64_t readNextNPC() { - panic("Alpha has no NextNPC!"); - return 0; + return this->readNextPC() + sizeof(TheISA::MachInst); } virtual void setNextNPC(uint64_t val) diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 5616ba398..7c8970299 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -659,9 +659,7 @@ FullO3CPU<Impl>::insertThread(unsigned tid) //Set PC/NPC/NNPC setPC(src_tc->readPC(), tid); setNextPC(src_tc->readNextPC(), tid); -#if ISA_HAS_DELAY_SLOT setNextNPC(src_tc->readNextNPC(), tid); -#endif src_tc->setStatus(ThreadContext::Active); diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 0da446c9c..baea7a546 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -219,11 +219,19 @@ class OzoneCPU : public BaseCPU uint64_t readNextNPC() { - return 0; +#if ISA_HAS_DELAY_SLOT + panic("Ozone needs to support nextNPC"); +#else + return thread->nextPC + sizeof(TheISA::MachInst); +#endif } void setNextNPC(uint64_t val) - { } + { +#if ISA_HAS_DELAY_SLOT + panic("Ozone needs to support nextNPC"); +#endif + } public: // ISA stuff: |