Add in Context IDs to the simulator. From now on, cpuId is almost never used,

the primary identifier for a hardware context should be contextId().  The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.

17 files changed, 59 insertions, 35 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 4845cbfaf..6409255f6 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -285,9 +285,9 @@ BaseCPU::registerThreadContexts()
     for (int i = 0; i < threadContexts.size(); ++i) {
         ThreadContext *tc = threadContexts[i];
 
-        system->registerThreadContext(tc);
+        tc->setContextId(system->registerThreadContext(tc));
 #if !FULL_SYSTEM
-        tc->getProcessPtr()->assignThreadContext(tc->cpuId());
+        tc->getProcessPtr()->assignThreadContext(tc->contextId());
 #endif
     }
 }
@@ -328,8 +328,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
 
         CpuEvent::replaceThreadContext(oldTC, newTC);
 
-        assert(newTC->cpuId() == oldTC->cpuId());
-        system->replaceThreadContext(newTC, newTC->cpuId());
+        assert(newTC->contextId() == oldTC->contextId());
+        system->replaceThreadContext(newTC, newTC->contextId());
 
         if (DTRACE(Context))
             ThreadContext::compare(oldTC, newTC);
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index e0de3a372..3520fafaa 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -414,6 +414,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Read this CPU's ID. */
     int cpuId() { return cpu->cpuId(); }
 
+    /** Read this context's system-wide ID **/
+    int contextId() { return thread->contextId(); }
+
     /** Returns the fault type. */
     Fault getFault() { return fault; }
 
@@ -868,7 +871,7 @@ BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
     reqMade = true;
     Request *req = new Request();
     req->setVirt(asid, vaddr, size, flags, PC);
-    req->setThreadContext(thread->cpuId(), threadNumber);
+    req->setThreadContext(thread->contextId(), threadNumber);
 
     fault = cpu->translateDataReadReq(req, thread);
 
@@ -887,7 +890,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
     reqMade = true;
     Request *req = new Request();
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
-    req->setThreadContext(thread->cpuId(), threadNumber);
+    req->setThreadContext(thread->contextId(), threadNumber);
 
     fault = cpu->translateDataReadReq(req, thread);
 
@@ -942,7 +945,7 @@ BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
     reqMade = true;
     Request *req = new Request();
     req->setVirt(asid, vaddr, size, flags, PC);
-    req->setThreadContext(thread->cpuId(), threadNumber);
+    req->setThreadContext(thread->contextId(), threadNumber);
 
     fault = cpu->translateDataWriteReq(req, thread);
 
@@ -966,7 +969,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
     reqMade = true;
     Request *req = new Request();
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
-    req->setThreadContext(thread->cpuId(), threadNumber);
+    req->setThreadContext(thread->contextId(), threadNumber);
 
     fault = cpu->translateDataWriteReq(req, thread);
 
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 9f6fa2b6d..0428e8806 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -152,7 +152,8 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
         memReq = new Request(inst->threadNumber, fetch_PC,
                              sizeof(uint32_t),
                              IFETCH_FLAGS(thread->readPC()),
-                             fetch_PC, thread->cpuId(), inst->threadNumber);
+                             fetch_PC, thread->contextId(),
+                             inst->threadNumber);
 
         bool succeeded = translateInstReq(memReq);
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b7cf4f1c0..26c155262 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -589,9 +589,7 @@ template <class Impl>
 void
 FullO3CPU<Impl>::init()
 {
-    if (!deferRegistration) {
-        registerThreadContexts();
-    }
+    BaseCPU::init();
 
     // Set inSyscall so that the CPU doesn't squash when initially
     // setting up registers.
@@ -610,7 +608,7 @@ FullO3CPU<Impl>::init()
         }
 
 #if FULL_SYSTEM
-        TheISA::initCPU(src_tc, src_tc->cpuId());
+        TheISA::initCPU(src_tc, src_tc->contextId());
 #endif
     }
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 35031663e..cff6db299 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -362,7 +362,7 @@ template<class Impl>
 void
 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
 {
-    unsigned tid = pkt->req->getThreadNum();
+    unsigned tid = pkt->req->threadId();
 
     DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
 
@@ -593,7 +593,8 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
     // Set the appropriate read size and flags as well.
     // Build request here.
     RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
-                                     fetch_PC, cpu->cpuId(), tid);
+                                     fetch_PC, cpu->thread[tid]->contextId(),
+                                     tid);
 
     memReq[tid] = mem_req;
 
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index f8a825726..cf27552d4 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -371,7 +371,7 @@ template <class T>
 Fault
 LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
 {
-    unsigned tid = req->getThreadNum();
+    unsigned tid = req->threadId();
 
     return thread[tid].read(req, data, load_idx);
 }
@@ -381,7 +381,7 @@ template <class T>
 Fault
 LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
 {
-    unsigned tid = req->getThreadNum();
+    unsigned tid = req->threadId();
 
     return thread[tid].write(req, data, store_idx);
 }
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 5aea020a9..8f9f63081 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -85,7 +85,7 @@ LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
     if (pkt->isError())
         DPRINTF(LSQ, "Got error packet back for address: %#X\n", pkt->getAddr());
     if (pkt->isResponse()) {
-        lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
+        lsq->thread[pkt->req->threadId()].completeDataAccess(pkt);
     }
     else {
         // must be a snoop
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index d571d25db..c237b9587 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -78,6 +78,10 @@ class O3ThreadContext : public ThreadContext
     /** Reads this CPU's ID. */
     virtual int cpuId() { return cpu->cpuId(); }
 
+    virtual int contextId() { return thread->contextId(); }
+
+    virtual void setContextId(int id) { thread->setContextId(id); }
+
 #if FULL_SYSTEM
     /** Returns a pointer to the system. */
     virtual System *getSystemPtr() { return cpu->system; }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 853ee2c63..50f6e58b3 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -63,6 +63,7 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
     // copy over functional state
     setStatus(old_context->status());
     copyArchRegs(old_context);
+    setContextId(old_context->contextId());
 
 #if !FULL_SYSTEM
     thread->funcExeInst = old_context->readFuncExeInst();
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 52376afd8..eef1a7b2f 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -417,7 +417,7 @@ OzoneCPU<Impl>::init()
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(tc, tc->cpuId());
+        TheISA::initCPU(tc, tc->contextId());
     }
 #endif
     frontEnd->renameTable.copyFrom(thread.renameTable);
@@ -736,14 +736,6 @@ OzoneCPU<Impl>::OzoneTC::getCpuPtr()
 
 template <class Impl>
 void
-OzoneCPU<Impl>::OzoneTC::setCpuId(int id)
-{
-    cpu->cpuId = id;
-    thread->setCpuId(id);
-}
-
-template <class Impl>
-void
 OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
 {
     thread->setStatus(new_status);
@@ -804,6 +796,7 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
     setStatus(old_context->status());
     copyArchRegs(old_context);
     setCpuId(old_context->cpuId());
+    setContextId(old_context->contextId());
 
     thread->setInst(old_context->getInst());
 #if !FULL_SYSTEM
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index df3609e27..b1e131115 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -477,7 +477,7 @@ FrontEnd<Impl>::fetchCacheLine()
     // Setup the memReq to do a read of the first isntruction's address.
     // Set the appropriate read size and flags as well.
     memReq = new Request(0, fetch_PC, cacheBlkSize, 0,
-                         PC, cpu->cpuId(), 0);
+                         PC, cpu->thread->contextId());
 
     // Translate the instruction request.
     fault = cpu->translateInstReq(memReq, thread);
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 5e8ab9443..feb8a7fc5 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -84,7 +84,7 @@ AtomicSimpleCPU::init()
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(tc, _cpuId);
+        TheISA::initCPU(tc, tc->contextId());
     }
 #endif
     if (hasPhysMemPort) {
@@ -93,6 +93,7 @@ AtomicSimpleCPU::init()
         physmemPort.getPeerAddressRanges(pmAddrList, snoop);
         physMemAddr = *pmAddrList.begin();
     }
+    // Atomic doesn't do MT right now, so contextId == threadId
     ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
     data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
     data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 247899ca8..ca1f0283e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -202,7 +202,6 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         _status = Idle;
     }
     assert(threadContexts.size() == 1);
-    _cpuId = tc->cpuId();
     previousTick = curTick;
 }
 
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 6034ca120..5c6b729b6 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -182,6 +182,8 @@ SimpleThread::copyState(ThreadContext *oldContext)
     funcExeInst = oldContext->readFuncExeInst();
 #endif
     inst = oldContext->getInst();
+
+    _contextId = oldContext->contextId();
 }
 
 void
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 58912c564..ab105a435 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -78,4 +78,11 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
     int id2 = two->cpuId();
     if (id1 != id2)
         panic("CPU ids don't match, one: %d, two: %d", id1, id2);
+
+    id1 = one->contextId();
+    id2 = two->contextId();
+    if (id1 != id2)
+        panic("Context ids don't match, one: %d, two: %d", id1, id2);
+
+
 }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index d06194012..a94be7024 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -117,6 +117,12 @@ class ThreadContext
 
     virtual int cpuId() = 0;
 
+    virtual int getThreadNum() = 0;
+
+    virtual int contextId() = 0;
+
+    virtual void setContextId(int id) = 0;
+
     virtual TheISA::ITB *getITBPtr() = 0;
 
     virtual TheISA::DTB *getDTBPtr() = 0;
@@ -177,8 +183,6 @@ class ThreadContext
     virtual void profileSample() = 0;
 #endif
 
-    virtual int getThreadNum() = 0;
-
     // Also somewhat obnoxious.  Really only used for the TLB fault.
     // However, may be quite useful in SPARC.
     virtual TheISA::MachInst getInst() = 0;
@@ -300,6 +304,12 @@ class ProxyThreadContext : public ThreadContext
 
     int cpuId() { return actualTC->cpuId(); }
 
+    int getThreadNum() { return actualTC->getThreadNum(); }
+
+    int contextId() { return actualTC->contextId(); }
+
+    void setContextId(int id) { actualTC->setContextId(id); }
+
     TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
 
     TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
@@ -360,9 +370,6 @@ class ProxyThreadContext : public ThreadContext
     void profileClear() { return actualTC->profileClear(); }
     void profileSample() { return actualTC->profileSample(); }
 #endif
-
-    int getThreadNum() { return actualTC->getThreadNum(); }
-
     // @todo: Do I need this?
     MachInst getInst() { return actualTC->getInst(); }
 
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index f3f154de3..fdb2ab0ab 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -80,6 +80,10 @@ struct ThreadState {
 
     int cpuId() { return baseCpu->cpuId(); }
 
+    int contextId() { return _contextId; }
+
+    void setContextId(int id) { _contextId = id; }
+
     void setTid(int id) { tid = id; }
 
     int readTid() { return tid; }
@@ -169,6 +173,9 @@ struct ThreadState {
     // Pointer to the base CPU.
     BaseCPU *baseCpu;
 
+    // system wide HW context id
+    int _contextId;
+
     // Index of hardware thread context on the CPU that this represents.
     int tid;