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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-05-12 15:11:44 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-05-12 15:11:44 -0700 |
| commit | debf04aef1b0f662e981507545cdac956dd22a47 (patch) | |
| tree | 46cdd72ebfecac8445eb357c3505b7efe47ab01e /src/cpu | |
| parent | 6d199f0b25e2e8c46f626187bb6f5f06d7bcc55c (diff) | |
| download | gem5-debf04aef1b0f662e981507545cdac956dd22a47.tar.xz | |
Make sure all addresses used in syscalls are truncated to 32 bits. Actually -all- arguements are truncated to 32 bits, but we should be able to get away with it.
--HG--
extra : convert_revision : 3b8766c68a4ab36e2e769fac4812657f3f7e0d1c
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/o3/sparc/cpu_impl.hh | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 50d980f55..2e398577e 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -272,7 +272,10 @@ SparcO3CPU<Impl>::getSyscallArg(int i, int tid) { TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), SparcISA::ArgumentReg0 + i); - return this->readArchIntReg(idx, tid); + TheISA::IntReg val = this->readArchIntReg(idx, tid); + if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) + val = bits(val, 31, 0); + return val; } template <class Impl> |