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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-24 11:46:39 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-24 11:46:39 -0500
commit485d103255c0f64ebf697650c899fe7a80db1d6d (patch)
tree3826b9e0a3d340a4318bb4900ded5742734824aa /src/cpu
parent9e3c8de30bafe33f35e4b9e82fb49418941f8cb7 (diff)
downloadgem5-485d103255c0f64ebf697650c899fe7a80db1d6d.tar.xz
MEM: Move all read/write blob functions from Port to PortProxy
This patch moves the readBlob/writeBlob/memsetBlob from the Port class to the PortProxy class, thus making a clear separation of the basic port functionality (recv/send functional/atomic/timing), and the higher-level functional accessors available on the port proxies. There are only a few places in the code base where the blob functions were used on ports, and they are all for peeking into the memory system without making a normal memory access (in the memtest, and the malta and tsunami pchip). The memtest also exemplifies how easy it is to create a non-translating proxy if desired. The malta and tsunami pchip used a slave port to perform a functional read, and this is now changed to rely on the physProxy of the system (to which they already have a pointer).
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/testers/memtest/memtest.cc5
-rw-r--r--src/cpu/testers/memtest/memtest.hh2
2 files changed, 5 insertions, 2 deletions
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index 2d0131a92..dffaa71ed 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -125,6 +125,7 @@ MemTest::MemTest(const Params *p)
tickEvent(this),
cachePort("test", this),
funcPort("functional", this),
+ funcProxy(funcPort),
retryPkt(NULL),
// mainMem(main_mem),
// checkMem(check_mem),
@@ -237,7 +238,7 @@ MemTest::completeRequest(PacketPtr pkt)
exitSimLoop("maximum number of loads reached");
} else {
assert(pkt->isWrite());
- funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
+ funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize());
numWrites++;
numWritesStat++;
}
@@ -349,7 +350,7 @@ MemTest::tick()
outstandingAddrs.insert(paddr);
// ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
- funcPort.readBlob(req->getPaddr(), result, req->getSize());
+ funcProxy.readBlob(req->getPaddr(), result, req->getSize());
DPRINTF(MemTest,
"id %d initiating %sread at addr %x (blk %x) expecting %x\n",
diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh
index 208b34caf..c56a37574 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -38,6 +38,7 @@
#include "base/statistics.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
+#include "mem/port_proxy.hh"
#include "params/MemTest.hh"
#include "sim/eventq.hh"
#include "sim/sim_exit.hh"
@@ -108,6 +109,7 @@ class MemTest : public MemObject
CpuPort cachePort;
CpuPort funcPort;
+ PortProxy funcProxy;
class MemTestSenderState : public Packet::SenderState, public FastAlloc
{