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authorAli Saidi <Ali.Saidi@ARM.com>2012-09-25 11:49:40 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2012-09-25 11:49:40 -0500
commit5adb4ddc126385567f602568c5ddbaa1d6fe1d6f (patch)
tree61289a1a4efcd38bf6b5add005193a92eb7c7c81 /src/cpu
parent396600de107220db8c2c8f3951eeb7062ac0e81c (diff)
downloadgem5-5adb4ddc126385567f602568c5ddbaa1d6fe1d6f.tar.xz
O3: Pack the comm structures a bit better to reduce their size.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/o3/comm.hh113
1 files changed, 62 insertions, 51 deletions
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index 31d252c73..587e1d9e7 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -121,12 +121,12 @@ template<class Impl>
struct TimeBufStruct {
typedef typename Impl::DynInstPtr DynInstPtr;
struct decodeComm {
- uint64_t branchAddr;
- InstSeqNum doneSeqNum;
+ TheISA::PCState nextPC;
DynInstPtr mispredictInst;
DynInstPtr squashInst;
+ InstSeqNum doneSeqNum;
Addr mispredPC;
- TheISA::PCState nextPC;
+ uint64_t branchAddr;
unsigned branchCount;
bool squash;
bool predIncorrect;
@@ -143,9 +143,7 @@ struct TimeBufStruct {
struct iewComm {
// Also eventually include skid buffer space.
- bool usedIQ;
unsigned freeIQEntries;
- bool usedLSQ;
unsigned freeLSQEntries;
unsigned iqCount;
@@ -153,57 +151,70 @@ struct TimeBufStruct {
unsigned dispatched;
unsigned dispatchedToLSQ;
+ bool usedIQ;
+ bool usedLSQ;
};
iewComm iewInfo[Impl::MaxThreads];
struct commitComm {
-
- /////////////// For Decode, IEW, Rename, Fetch ///////////
- bool squash;
- bool robSquashing;
-
- ////////// For Fetch & IEW /////////////
- // Represents the instruction that has either been retired or
- // squashed. Similar to having a single bus that broadcasts the
- // retired or squashed sequence number.
- InstSeqNum doneSeqNum;
-
- ////////////// For Rename /////////////////
- // Rename should re-read number of free rob entries
- bool usedROB;
- // Notify Rename that the ROB is empty
- bool emptyROB;
- // Tell Rename how many free entries it has in the ROB
- unsigned freeROBEntries;
-
-
- ///////////// For Fetch //////////////////
- // Provide fetch the instruction that mispredicted, if this
- // pointer is not-null a misprediction occured
- DynInstPtr mispredictInst;
- // Was the branch taken or not
- bool branchTaken;
- // The pc of the next instruction to execute. This is the next
- // instruction for a branch mispredict, but the same instruction for
- // order violation and the like
- TheISA::PCState pc;
-
- // Instruction that caused the a non-mispredict squash
- DynInstPtr squashInst;
- // If an interrupt is pending and fetch should stall
- bool interruptPending;
- // If the interrupt ended up being cleared before being handled
- bool clearInterrupt;
-
- //////////// For IEW //////////////////
- // Communication specifically to the IQ to tell the IQ that it can
- // schedule a non-speculative instruction.
- InstSeqNum nonSpecSeqNum;
-
- // Hack for now to send back an uncached access to the IEW stage.
- bool uncached;
- DynInstPtr uncachedLoad;
+ /////////////////////////////////////////////////////////////////////
+ // This code has been re-structured for better packing of variables
+ // instead of by stage which is the more logical way to arrange the
+ // data.
+ // F = Fetch
+ // D = Decode
+ // I = IEW
+ // R = Rename
+ // As such each member is annotated with who consumes it
+ // e.g. bool variable name // *F,R for Fetch and Rename
+ /////////////////////////////////////////////////////////////////////
+
+ /// The pc of the next instruction to execute. This is the next
+ /// instruction for a branch mispredict, but the same instruction for
+ /// order violation and the like
+ TheISA::PCState pc; // *F
+
+ /// Provide fetch the instruction that mispredicted, if this
+ /// pointer is not-null a misprediction occured
+ DynInstPtr mispredictInst; // *F
+
+ /// Instruction that caused the a non-mispredict squash
+ DynInstPtr squashInst; // *F
+
+ /// Hack for now to send back an uncached access to the IEW stage.
+ DynInstPtr uncachedLoad; // *I
+
+ /// Communication specifically to the IQ to tell the IQ that it can
+ /// schedule a non-speculative instruction.
+ InstSeqNum nonSpecSeqNum; // *I
+
+ /// Represents the instruction that has either been retired or
+ /// squashed. Similar to having a single bus that broadcasts the
+ /// retired or squashed sequence number.
+ InstSeqNum doneSeqNum; // *F, I
+
+ /// Tell Rename how many free entries it has in the ROB
+ unsigned freeROBEntries; // *R
+
+ bool squash; // *F, D, R, I
+ bool robSquashing; // *F, D, R, I
+
+ /// Rename should re-read number of free rob entries
+ bool usedROB; // *R
+
+ /// Notify Rename that the ROB is empty
+ bool emptyROB; // *R
+
+ /// Was the branch taken or not
+ bool branchTaken; // *F
+ /// If an interrupt is pending and fetch should stall
+ bool interruptPending; // *F
+ /// If the interrupt ended up being cleared before being handled
+ bool clearInterrupt; // *F
+
+ /// Hack for now to send back an uncached access to the IEW stage.
+ bool uncached; // *I
};