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authorGeoffrey Blake <geoffrey.blake@arm.com>2012-03-09 09:59:28 -0500
committerGeoffrey Blake <geoffrey.blake@arm.com>2012-03-09 09:59:28 -0500
commit98cf57fb89b76a8ca423083d52cc647c7923fe51 (patch)
tree0376266c9e2b9381354bf86b3c7f2db4981577ea /src/cpu
parent043709fdfab3b6c46f6ef95d1f642cd3c06ee20a (diff)
downloadgem5-98cf57fb89b76a8ca423083d52cc647c7923fe51.tar.xz
CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible with ISAs other than ARM. This patch adds the appropriate function stubs to allow compilation.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/checker/cpu.hh14
-rw-r--r--src/cpu/checker/cpu_impl.hh17
-rw-r--r--src/cpu/inorder/thread_context.hh13
3 files changed, 39 insertions, 5 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index c3d3a379e..afc453f87 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -311,6 +311,20 @@ class CheckerCPU : public BaseCPU
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->setMiscReg(reg_idx, val);
}
+
+#if THE_ISA == MIPS_ISA
+ uint64_t readRegOtherThread(int misc_reg)
+ {
+ panic("MIPS MT not defined for CheckerCPU.\n");
+ return 0;
+ }
+
+ void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
+ {
+ panic("MIPS MT not defined for CheckerCPU.\n");
+ }
+#endif
+
/////////////////////////////////////////
void recordPCChange(const TheISA::PCState &val)
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 4f3fa34d2..167c3531f 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -44,6 +44,7 @@
#include <list>
#include <string>
+#include "arch/isa_traits.hh"
#include "arch/vtophys.hh"
#include "base/refcnt.hh"
#include "config/the_isa.hh"
@@ -201,9 +202,9 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
// maintain $r0 semantics
thread->setIntReg(ZeroReg, 0);
-#ifdef TARGET_ALPHA
- thread->setFloatRegDouble(ZeroReg, 0.0);
-#endif // TARGET_ALPHA
+#if THE_ISA == ALPHA_ISA
+ thread->setFloatReg(ZeroReg, 0.0);
+#endif
// Check if any recent PC changes match up with anything we
// expect to happen. This is mostly to check if traps or
@@ -320,7 +321,9 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
thread->pcState(pcState);
instPtr = thread->decoder.decode(newMachInst,
pcState.instAddr());
- machInst = newMachInst;
+#if THE_ISA != X86_ISA
+ machInst = newMachInst;
+#endif
} else {
fetchDone = false;
fetchOffset += sizeof(TheISA::MachInst);
@@ -476,7 +479,11 @@ Checker<Impl>::validateInst(DynInstPtr &inst)
}
}
- MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
+
+ MachInst mi;
+#if THE_ISA != X86_ISA
+ mi = static_cast<MachInst>(inst->staticInst->machInst);
+#endif
if (mi != machInst) {
panic("%lli: Binary instructions do not match! Inst: %#x, "
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 0f9b1028e..aaf7d6ede 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -40,6 +40,7 @@
#include "arch/kernel_stats.hh"
class EndQuiesceEvent;
+class CheckerCPU;
namespace Kernel {
class Statistics;
};
@@ -76,6 +77,12 @@ class InOrderThreadContext : public ThreadContext
/** @TODO: PERF: Should we bind this to a pointer in constructor? */
TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
+ /** Currently InOrder model does not support CheckerCPU, this is
+ * merely here for supporting compilation of gem5 with the Checker
+ * as a runtime option
+ */
+ CheckerCPU *getCheckerCpuPtr() { return NULL; }
+
Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
System *getSystemPtr() { return cpu->system; }
@@ -215,6 +222,12 @@ class InOrderThreadContext : public ThreadContext
void pcState(const TheISA::PCState &val)
{ cpu->pcState(val, thread->threadId()); }
+ /** Needs to be implemented for future CheckerCPU support.
+ * See O3CPU for examples on how to integrate Checker.
+ */
+ void pcStateNoRecord(const TheISA::PCState &val)
+ {}
+
Addr instAddr()
{ return cpu->instAddr(thread->threadId()); }