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authorAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:08:08 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:08:08 -0400
commit1c321b88473d65ff4bd9a7b65a91351781fd31d8 (patch)
tree0a1ec8860927b8f453c42b3997fcde1979a43939 /src/cpu
parenta850fc916f06f05c1c55d634cdb2b230a7c23d11 (diff)
downloadgem5-1c321b88473d65ff4bd9a7b65a91351781fd31d8.tar.xz
Regression: Use CPU clock and 32-byte width for L1-L2 bus
This patch changes the CoherentBus between the L1s and L2 to use the CPU clock and also four times the width compared to the default bus. The parameters are not intending to fit every single scenario, but rather serve as a better startingpoint than what we previously had. Note that the scripts that do not use the addTwoLevelCacheHiearchy are not affected by this change. A separate patch will update the stats.
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/BaseCPU.py5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 6e5f6ff1a..331957749 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -236,7 +236,10 @@ class BaseCPU(MemObject):
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
- self.toL2Bus = CoherentBus()
+ # Override the default bus clock of 1 GHz and uses the CPU
+ # clock for the L1-to-L2 bus, and also set a width of 32 bytes
+ # (256-bits), which is four times that of the default bus.
+ self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
self.toL2Bus.master = self.l2cache.cpu_side