arch: cpu: Stop passing around misc registers by reference.

These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.

Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12 files changed, 29 insertions, 34 deletions

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 2c7e022bd..4468689bd 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -417,7 +417,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
 
     void
-    setMiscRegNoEffect(int misc_reg, const RegVal &val)
+    setMiscRegNoEffect(int misc_reg, RegVal val)
     {
         DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
                 misc_reg);
@@ -426,7 +426,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
 
     void
-    setMiscReg(int misc_reg, const RegVal &val) override
+    setMiscReg(int misc_reg, RegVal val) override
     {
         DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
                 misc_reg);
@@ -443,8 +443,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
 
     void
-    setMiscRegOperand(const StaticInst *si, int idx,
-                      const RegVal &val) override
+    setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isMiscReg());
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 854771fdd..b5a2079ea 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -348,7 +348,7 @@ class CheckerThreadContext : public ThreadContext
     { return actualTC->readMiscReg(misc_reg); }
 
     void
-    setMiscRegNoEffect(int misc_reg, const RegVal &val)
+    setMiscRegNoEffect(int misc_reg, RegVal val)
     {
         DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
                          " and O3..\n", misc_reg);
@@ -357,7 +357,7 @@ class CheckerThreadContext : public ThreadContext
     }
 
     void
-    setMiscReg(int misc_reg, const RegVal &val)
+    setMiscReg(int misc_reg, RegVal val)
     {
         DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
                          " and O3..\n", misc_reg);
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 0fe4a731a..75f428b87 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -182,7 +182,7 @@ class ExecContext {
      */
     virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
     virtual void setMiscRegOperand(const StaticInst *si,
-                                   int idx, const RegVal &val) = 0;
+                                   int idx, RegVal val) = 0;
 
     /**
      * Reads a miscellaneous register, handling any architectural
@@ -194,7 +194,7 @@ class ExecContext {
      * Sets a miscellaneous register, handling any architectural
      * side effects due to writing that register.
      */
-    virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
+    virtual void setMiscReg(int misc_reg, RegVal val) = 0;
 
     /** @} */
 
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 9f8e9f7af..76d46e905 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -309,7 +309,7 @@ class ExecContext : public ::ExecContext
     }
 
     void
-    setMiscReg(int misc_reg, const RegVal &val) override
+    setMiscReg(int misc_reg, RegVal val) override
     {
         thread.setMiscReg(misc_reg, val);
     }
@@ -323,8 +323,7 @@ class ExecContext : public ::ExecContext
     }
 
     void
-    setMiscRegOperand(const StaticInst *si, int idx,
-                      const RegVal &val) override
+    setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isMiscReg());
@@ -431,7 +430,7 @@ class ExecContext : public ::ExecContext
     }
 
     void
-    setRegOtherThread(const RegId &reg, const RegVal &val,
+    setRegOtherThread(const RegId &reg, RegVal val,
                       ThreadID tid=InvalidThreadID)
     {
         SimpleThread *other_thread = (tid == InvalidThreadID
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c65e509f9..600c89aa5 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1260,16 +1260,14 @@ FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
-        const RegVal &val, ThreadID tid)
+FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
 {
     this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
 }
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setMiscReg(int misc_reg,
-        const RegVal &val, ThreadID tid)
+FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
 {
     miscRegfileWrites++;
     this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 431eb0f2f..90024bc84 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -390,12 +390,12 @@ class FullO3CPU : public BaseO3CPU
     RegVal readMiscReg(int misc_reg, ThreadID tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid);
+    void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid);
+    void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
 
     RegVal readIntReg(PhysRegIdPtr phys_reg);
 
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 9054b2089..5bd0f8e47 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -146,7 +146,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      * might have as defined by the architecture.
      */
     void
-    setMiscReg(int misc_reg, const RegVal &val)
+    setMiscReg(int misc_reg, RegVal val)
     {
         /** Writes to misc. registers are recorded and deferred until the
          * commit stage, when updateMiscRegs() is called. First, check if
@@ -182,7 +182,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
      * might have as defined by the architecture.
      */
     void
-    setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val)
+    setMiscRegOperand(const StaticInst *si, int idx, RegVal val)
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isMiscReg());
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 510e96432..c74936469 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -331,11 +331,11 @@ class O3ThreadContext : public ThreadContext
     { return cpu->readMiscReg(misc_reg, thread->threadId()); }
 
     /** Sets a misc. register. */
-    virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val);
+    virtual void setMiscRegNoEffect(int misc_reg, RegVal val);
 
     /** Sets a misc. register, including any side-effects the
      * write might have as defined by the architecture. */
-    virtual void setMiscReg(int misc_reg, const RegVal &val);
+    virtual void setMiscReg(int misc_reg, RegVal val);
 
     virtual RegId flattenRegId(const RegId& regId) const;
 
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 086d2cfeb..e1d771740 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -307,7 +307,7 @@ O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
+O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val)
 {
     cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
 
@@ -317,7 +317,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
 #endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
 template <class Impl>
 void
-O3ThreadContext<Impl>::setMiscReg(int misc_reg, const RegVal &val)
+O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val)
 {
     cpu->setMiscReg(misc_reg, val, thread->threadId());
 
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index aa6ee8ba3..7db7d20d9 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -361,8 +361,7 @@ class SimpleExecContext : public ExecContext {
     }
 
     void
-    setMiscRegOperand(const StaticInst *si, int idx,
-                      const RegVal &val) override
+    setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         numIntRegWrites++;
         const RegId& reg = si->destRegIdx(idx);
@@ -386,7 +385,7 @@ class SimpleExecContext : public ExecContext {
      * side effects due to writing that register.
      */
     void
-    setMiscReg(int misc_reg, const RegVal &val) override
+    setMiscReg(int misc_reg, RegVal val) override
     {
         numIntRegWrites++;
         thread->setMiscReg(misc_reg, val);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 073f7ab2c..211a4c89f 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -489,13 +489,13 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0)
+    setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0)
     {
         return isa->setMiscRegNoEffect(misc_reg, val);
     }
 
     void
-    setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0)
+    setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0)
     {
         return isa->setMiscReg(misc_reg, val, tc);
     }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index db88227d9..cad073b4f 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -278,9 +278,9 @@ class ThreadContext
 
     virtual RegVal readMiscReg(int misc_reg) = 0;
 
-    virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val) = 0;
+    virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0;
 
-    virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
+    virtual void setMiscReg(int misc_reg, RegVal val) = 0;
 
     virtual RegId flattenRegId(const RegId& regId) const = 0;
 
@@ -291,7 +291,7 @@ class ThreadContext
     }
 
     virtual void
-    setRegOtherThread(const RegId& misc_reg, const RegVal &val, ThreadID tid)
+    setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
     {
     }
 
@@ -541,10 +541,10 @@ class ProxyThreadContext : public ThreadContext
     RegVal readMiscReg(int misc_reg)
     { return actualTC->readMiscReg(misc_reg); }
 
-    void setMiscRegNoEffect(int misc_reg, const RegVal &val)
+    void setMiscRegNoEffect(int misc_reg, RegVal val)
     { return actualTC->setMiscRegNoEffect(misc_reg, val); }
 
-    void setMiscReg(int misc_reg, const RegVal &val)
+    void setMiscReg(int misc_reg, RegVal val)
     { return actualTC->setMiscReg(misc_reg, val); }
 
     RegId flattenRegId(const RegId& regId) const