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authorNathan Binkert <nate@binkert.org>2009-06-04 21:50:20 -0700
committerNathan Binkert <nate@binkert.org>2009-06-04 21:50:20 -0700
commit4e3426624557b555c354035ee3961eab7554d81d (patch)
tree7d5e73630456de787526292b754224e918a4b823 /src/cpu
parente30c62ad994a730b78361b5ecce45b97e58c0701 (diff)
downloadgem5-4e3426624557b555c354035ee3961eab7554d81d.tar.xz
move: put predictor includes and cc files into the same place
--HG-- rename : src/cpu/2bit_local_pred.cc => src/cpu/pred/2bit_local.cc rename : src/cpu/o3/2bit_local_pred.hh => src/cpu/pred/2bit_local.hh rename : src/cpu/btb.cc => src/cpu/pred/btb.cc rename : src/cpu/o3/btb.hh => src/cpu/pred/btb.hh rename : src/cpu/ras.cc => src/cpu/pred/ras.cc rename : src/cpu/o3/ras.hh => src/cpu/pred/ras.hh rename : src/cpu/tournament_pred.cc => src/cpu/pred/tournament.cc rename : src/cpu/o3/tournament_pred.hh => src/cpu/pred/tournament.hh
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/SConscript7
-rw-r--r--src/cpu/inorder/resources/bpred_unit.hh17
-rw-r--r--src/cpu/o3/bpred_unit.hh8
-rw-r--r--src/cpu/pred/2bit_local.cc (renamed from src/cpu/2bit_local_pred.cc)2
-rw-r--r--src/cpu/pred/2bit_local.hh (renamed from src/cpu/o3/2bit_local_pred.hh)0
-rw-r--r--src/cpu/pred/SConscript38
-rw-r--r--src/cpu/pred/btb.cc (renamed from src/cpu/btb.cc)2
-rw-r--r--src/cpu/pred/btb.hh (renamed from src/cpu/o3/btb.hh)0
-rw-r--r--src/cpu/pred/ras.cc (renamed from src/cpu/ras.cc)2
-rw-r--r--src/cpu/pred/ras.hh (renamed from src/cpu/o3/ras.hh)0
-rw-r--r--src/cpu/pred/tournament.cc (renamed from src/cpu/tournament_pred.cc)2
-rw-r--r--src/cpu/pred/tournament.hh (renamed from src/cpu/o3/tournament_pred.hh)0
12 files changed, 53 insertions, 25 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 80bc0986e..44f8817ff 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -126,13 +126,6 @@ Source('simple_thread.cc')
Source('thread_context.cc')
Source('thread_state.cc')
-if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS']:
- Source('btb.cc')
- Source('tournament_pred.cc')
- Source('2bit_local_pred.cc')
- Source('ras.cc')
- TraceFlag('FreeList')
-
if env['FULL_SYSTEM']:
SimObject('IntrControl.py')
diff --git a/src/cpu/inorder/resources/bpred_unit.hh b/src/cpu/inorder/resources/bpred_unit.hh
index abbb70e0d..1571e3206 100644
--- a/src/cpu/inorder/resources/bpred_unit.hh
+++ b/src/cpu/inorder/resources/bpred_unit.hh
@@ -32,21 +32,18 @@
#ifndef __CPU_INORDER_BPRED_UNIT_HH__
#define __CPU_INORDER_BPRED_UNIT_HH__
-// For Addr type.
+#include <list>
+
#include "arch/isa_traits.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
-
-//#include "cpu/inorder/params.hh"
-#include "cpu/o3/2bit_local_pred.hh"
-#include "cpu/o3/btb.hh"
-#include "cpu/o3/ras.hh"
-#include "cpu/o3/tournament_pred.hh"
-#include "params/InOrderCPU.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
-
-#include <list>
+#include "cpu/pred/2bit_local.hh"
+#include "cpu/pred/btb.hh"
+#include "cpu/pred/ras.hh"
+#include "cpu/pred/tournament.hh"
+#include "params/InOrderCPU.hh"
/**
* Basically a wrapper class to hold both the branch predictor
diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh
index 49cb4233b..f199bdd75 100644
--- a/src/cpu/o3/bpred_unit.hh
+++ b/src/cpu/o3/bpred_unit.hh
@@ -36,10 +36,10 @@
#include "base/statistics.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
-#include "cpu/o3/2bit_local_pred.hh"
-#include "cpu/o3/btb.hh"
-#include "cpu/o3/ras.hh"
-#include "cpu/o3/tournament_pred.hh"
+#include "cpu/pred/2bit_local.hh"
+#include "cpu/pred/btb.hh"
+#include "cpu/pred/ras.hh"
+#include "cpu/pred/tournament.hh"
class DerivO3CPUParams;
diff --git a/src/cpu/2bit_local_pred.cc b/src/cpu/pred/2bit_local.cc
index 77a45ea26..65925fe79 100644
--- a/src/cpu/2bit_local_pred.cc
+++ b/src/cpu/pred/2bit_local.cc
@@ -31,7 +31,7 @@
#include "base/intmath.hh"
#include "base/misc.hh"
#include "base/trace.hh"
-#include "cpu/o3/2bit_local_pred.hh"
+#include "cpu/pred/2bit_local.hh"
LocalBP::LocalBP(unsigned _localPredictorSize,
unsigned _localCtrBits,
diff --git a/src/cpu/o3/2bit_local_pred.hh b/src/cpu/pred/2bit_local.hh
index 8b7bb8463..8b7bb8463 100644
--- a/src/cpu/o3/2bit_local_pred.hh
+++ b/src/cpu/pred/2bit_local.hh
diff --git a/src/cpu/pred/SConscript b/src/cpu/pred/SConscript
new file mode 100644
index 000000000..ce1dab9e2
--- /dev/null
+++ b/src/cpu/pred/SConscript
@@ -0,0 +1,38 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+Import('*')
+
+if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS']:
+ Source('2bit_local.cc')
+ Source('btb.cc')
+ Source('ras.cc')
+ Source('tournament.cc')
+ TraceFlag('FreeList')
diff --git a/src/cpu/btb.cc b/src/cpu/pred/btb.cc
index 4c1d441be..81676aceb 100644
--- a/src/cpu/btb.cc
+++ b/src/cpu/pred/btb.cc
@@ -30,7 +30,7 @@
#include "base/intmath.hh"
#include "base/trace.hh"
-#include "cpu/o3/btb.hh"
+#include "cpu/pred/btb.hh"
DefaultBTB::DefaultBTB(unsigned _numEntries,
unsigned _tagBits,
diff --git a/src/cpu/o3/btb.hh b/src/cpu/pred/btb.hh
index 6557522e0..6557522e0 100644
--- a/src/cpu/o3/btb.hh
+++ b/src/cpu/pred/btb.hh
diff --git a/src/cpu/ras.cc b/src/cpu/pred/ras.cc
index f9939259a..5af188749 100644
--- a/src/cpu/ras.cc
+++ b/src/cpu/pred/ras.cc
@@ -28,7 +28,7 @@
* Authors: Kevin Lim
*/
-#include "cpu/o3/ras.hh"
+#include "cpu/pred/ras.hh"
void
ReturnAddrStack::init(unsigned _numEntries)
diff --git a/src/cpu/o3/ras.hh b/src/cpu/pred/ras.hh
index a36faf79a..a36faf79a 100644
--- a/src/cpu/o3/ras.hh
+++ b/src/cpu/pred/ras.hh
diff --git a/src/cpu/tournament_pred.cc b/src/cpu/pred/tournament.cc
index ffb941c77..223e45333 100644
--- a/src/cpu/tournament_pred.cc
+++ b/src/cpu/pred/tournament.cc
@@ -29,7 +29,7 @@
*/
#include "base/intmath.hh"
-#include "cpu/o3/tournament_pred.hh"
+#include "cpu/pred/tournament.hh"
TournamentBP::TournamentBP(unsigned _localPredictorSize,
unsigned _localCtrBits,
diff --git a/src/cpu/o3/tournament_pred.hh b/src/cpu/pred/tournament.hh
index 96bd43ed6..96bd43ed6 100644
--- a/src/cpu/o3/tournament_pred.hh
+++ b/src/cpu/pred/tournament.hh