Decode: Make the Decoder class defined per ISA.

--HG--
rename : src/cpu/decode.cc => src/arch/generic/decoder.cc
rename : src/cpu/decode.hh => src/arch/generic/decoder.hh

14 files changed, 18 insertions, 110 deletions

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 922a2d9d7..e1ba59b8b 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -108,7 +108,6 @@ SimObject('NativeTrace.py')
 Source('activity.cc')
 Source('base.cc')
 Source('cpuevent.cc')
-Source('decode.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
 Source('inteltrace.cc')
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 710d827cc..0da73a137 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -55,6 +55,7 @@ namespace TheISA {
     namespace Kernel {
         class Statistics;
     };
+    class Decoder;
 };
 
 /**
@@ -117,7 +118,7 @@ class CheckerThreadContext : public ThreadContext
         return checkerCPU;
     }
 
-    Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 
     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 
diff --git a/src/cpu/decode.cc b/src/cpu/decode.cc
deleted file mode 100644
index 56a484b07..000000000
--- a/src/cpu/decode.cc
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2011 Google
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "cpu/decode.hh"
-
-DecodeCache<TheISA::decodeInst> Decoder::cache;
diff --git a/src/cpu/decode.hh b/src/cpu/decode.hh
deleted file mode 100644
index 653f8eea5..000000000
--- a/src/cpu/decode.hh
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2011 Google
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __CPU_DECODE_HH__
-#define __CPU_DECODE_HH__
-
-#include "arch/isa_traits.hh"
-#include "arch/types.hh"
-#include "config/the_isa.hh"
-#include "cpu/decode_cache.hh"
-#include "cpu/static_inst.hh"
-
-/// The decoder class. This class doesn't do much of anything now, but in the
-/// future it will be redefinable per ISA and allow more interesting behavior.
-class Decoder
-{
-  protected:
-    /// A cache of decoded instruction objects.
-    static DecodeCache<TheISA::decodeInst> cache;
-
-  public:
-    /// Decode a machine instruction.
-    /// @param mach_inst The binary instruction to decode.
-    /// @retval A pointer to the corresponding StaticInst object.
-    StaticInstPtr
-    decode(TheISA::ExtMachInst mach_inst, Addr addr)
-    {
-        return cache.decode(mach_inst, addr);
-    }
-};
-
-#endif // __CPU_DECODE_HH__
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 7e75dfbb8..9ad0a2680 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1772,7 +1772,7 @@ InOrderCPU::getDTBPtr()
     return resPool->getDataUnit()->tlb();
 }
 
-Decoder *
+TheISA::Decoder *
 InOrderCPU::getDecoderPtr()
 {
     return &resPool->getInstUnit()->decoder;
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index bb52c6023..29fe6bc3b 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -342,7 +342,7 @@ class InOrderCPU : public BaseCPU
     TheISA::TLB *getITBPtr();
     TheISA::TLB *getDTBPtr();
 
-    Decoder *getDecoderPtr();
+    TheISA::Decoder *getDecoderPtr();
 
     /** Accessor Type for the SkedCache */
     typedef uint32_t SkedID;
diff --git a/src/cpu/inorder/resources/fetch_unit.hh b/src/cpu/inorder/resources/fetch_unit.hh
index 6d734d7e6..eb99cd570 100644
--- a/src/cpu/inorder/resources/fetch_unit.hh
+++ b/src/cpu/inorder/resources/fetch_unit.hh
@@ -36,10 +36,10 @@
 #include <string>
 #include <vector>
 
+#include "arch/decoder.hh"
 #include "arch/predecoder.hh"
 #include "arch/tlb.hh"
 #include "config/the_isa.hh"
-#include "cpu/decode.hh"
 #include "cpu/inorder/resources/cache_unit.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
@@ -89,7 +89,7 @@ class FetchUnit : public CacheUnit
 
     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 
-    Decoder decoder;
+    TheISA::Decoder decoder;
 
   private:
     void squashCacheRequest(CacheReqPtr req_ptr);
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 6f9bc5dac..b7d0dda9c 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -83,7 +83,7 @@ class InOrderThreadContext : public ThreadContext
      */
     CheckerCPU *getCheckerCpuPtr() { return NULL; }
 
-    Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
+    TheISA::Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
 
     System *getSystemPtr() { return cpu->system; }
 
diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc
index 75d30c894..34c732c54 100644
--- a/src/cpu/legiontrace.cc
+++ b/src/cpu/legiontrace.cc
@@ -42,13 +42,13 @@
 #include <cstdio>
 #include <iomanip>
 
+#include "arch/sparc/decoder.hh"
 #include "arch/sparc/predecoder.hh"
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/utility.hh"
 #include "arch/tlb.hh"
 #include "base/socket.hh"
 #include "cpu/base.hh"
-#include "cpu/decode.hh"
 #include "cpu/legiontrace.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index b61ae2c7b..474834889 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -44,11 +44,11 @@
 #ifndef __CPU_O3_FETCH_HH__
 #define __CPU_O3_FETCH_HH__
 
+#include "arch/decoder.hh"
 #include "arch/predecoder.hh"
 #include "arch/utility.hh"
 #include "base/statistics.hh"
 #include "config/the_isa.hh"
-#include "cpu/decode.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/timebuf.hh"
 #include "cpu/translation.hh"
@@ -340,7 +340,7 @@ class DefaultFetch
     }
 
     /** The decoder. */
-    Decoder decoder;
+    TheISA::Decoder decoder;
 
   private:
     DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 178a344f9..b4108e25c 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -85,7 +85,7 @@ class O3ThreadContext : public ThreadContext
 
     CheckerCPU *getCheckerCpuPtr() { return NULL; }
 
-    Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
+    TheISA::Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
 
     /** Returns a pointer to this CPU. */
     virtual BaseCPU *getCpuPtr() { return cpu; }
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 67fbccf98..34b039fc0 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -45,12 +45,12 @@
 #ifndef __CPU_SIMPLE_BASE_HH__
 #define __CPU_SIMPLE_BASE_HH__
 
+#include "arch/decoder.hh"
 #include "arch/predecoder.hh"
 #include "base/statistics.hh"
 #include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
-#include "cpu/decode.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index b1b8a66e4..1595551fb 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -44,6 +44,7 @@
 #ifndef __CPU_SIMPLE_THREAD_HH__
 #define __CPU_SIMPLE_THREAD_HH__
 
+#include "arch/decoder.hh"
 #include "arch/isa.hh"
 #include "arch/isa_traits.hh"
 #include "arch/registers.hh"
@@ -51,7 +52,6 @@
 #include "arch/types.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
-#include "cpu/decode.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
 #include "debug/FloatRegs.hh"
@@ -128,7 +128,7 @@ class SimpleThread : public ThreadState
     TheISA::TLB *itb;
     TheISA::TLB *dtb;
 
-    Decoder decoder;
+    TheISA::Decoder decoder;
 
     // constructor: initialize SimpleThread from given process structure
     // FS
@@ -199,7 +199,7 @@ class SimpleThread : public ThreadState
 
     CheckerCPU *getCheckerCpuPtr() { return NULL; }
 
-    Decoder *getDecoderPtr() { return &decoder; }
+    TheISA::Decoder *getDecoderPtr() { return &decoder; }
 
     System *getSystemPtr() { return system; }
 
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 220c6cfc5..e186e2f83 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -55,12 +55,12 @@
 // DTB pointers.
 namespace TheISA
 {
+    class Decoder;
     class TLB;
 }
 class BaseCPU;
 class CheckerCPU;
 class Checkpoint;
-class Decoder;
 class EndQuiesceEvent;
 class SETranslatingPortProxy;
 class FSTranslatingPortProxy;
@@ -135,7 +135,7 @@ class ThreadContext
 
     virtual CheckerCPU *getCheckerCpuPtr() = 0;
 
-    virtual Decoder *getDecoderPtr() = 0;
+    virtual TheISA::Decoder *getDecoderPtr() = 0;
 
     virtual System *getSystemPtr() = 0;
 
@@ -306,7 +306,7 @@ class ProxyThreadContext : public ThreadContext
 
     CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
 
-    Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+    TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 
     System *getSystemPtr() { return actualTC->getSystemPtr(); }