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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
commit | a480ba00b96f4c2e872f5a01bfa1782500f1066e (patch) | |
tree | 9d99a96528f37eb601f6e7268c3a359d84f02d57 /src/cpu | |
parent | 0cb180ea0dcece9157ad71b4136d557c2dbcf209 (diff) | |
download | gem5-a480ba00b96f4c2e872f5a01bfa1782500f1066e.tar.xz |
Registers: Eliminate the ISA defined integer register file.
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/inorder/cpu.cc | 6 | ||||
-rw-r--r-- | src/cpu/inorder/cpu.hh | 2 | ||||
-rw-r--r-- | src/cpu/simple_thread.cc | 6 | ||||
-rw-r--r-- | src/cpu/simple_thread.hh | 7 |
4 files changed, 13 insertions, 8 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 248e78314..36de86986 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -264,7 +264,7 @@ InOrderCPU::InOrderCPU(Params *params) squashSeqNum[tid] = MaxAddr; lastSquashCycle[tid] = 0; - intRegFile[tid].clear(); + memset(intRegs[tid], 0, sizeof(intRegs[tid])); memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid])); isa[tid].clear(); @@ -886,7 +886,7 @@ InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid) uint64_t InOrderCPU::readIntReg(int reg_idx, ThreadID tid) { - return intRegFile[tid].readReg(reg_idx); + return intRegs[tid][reg_idx]; } FloatReg @@ -904,7 +904,7 @@ InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid) void InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid) { - intRegFile[tid].setReg(reg_idx, val); + intRegs[tid][reg_idx] = val; } diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index f4cc72e9c..31010a01f 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -258,11 +258,11 @@ class InOrderCPU : public BaseCPU TheISA::IntReg nextNPC[ThePipeline::MaxThreads]; /** The Register File for the CPU */ - TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];; union { FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; } floatRegs; + TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs]; /** ISA state */ TheISA::ISA isa[ThePipeline::MaxThreads]; diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 505222b37..d88e02ff1 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -71,7 +71,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, quiesceEvent = new EndQuiesceEvent(tc); - regs.clear(); + clearArchRegs(); if (cpu->params()->profile) { profile = new FunctionProfile(system->kernelSymtab); @@ -96,7 +96,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, : ThreadState(_cpu, _thread_num, _process, _asid), cpu(_cpu), itb(_itb), dtb(_dtb) { - regs.clear(); + clearArchRegs(); tc = new ProxyThreadContext<SimpleThread>(this); } @@ -193,6 +193,7 @@ SimpleThread::serialize(ostream &os) ThreadState::serialize(os); regs.serialize(cpu, os); SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); + SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); // thread_num and cpu_id are deterministic from the config } @@ -203,6 +204,7 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) ThreadState::unserialize(cp, section); regs.unserialize(cpu, cp, section); UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); + UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); // thread_num and cpu_id are deterministic from the config } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 5e29fbb6d..97c02d7b8 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -36,6 +36,7 @@ #include "arch/isa_traits.hh" #include "arch/regfile.hh" #include "arch/tlb.hh" +#include "arch/types.hh" #include "base/types.hh" #include "config/full_system.hh" #include "cpu/thread_context.hh" @@ -103,6 +104,7 @@ class SimpleThread : public ThreadState FloatReg f[TheISA::NumFloatRegs]; FloatRegBits i[TheISA::NumFloatRegs]; } floatRegs; + TheISA::IntReg intRegs[TheISA::NumIntRegs]; TheISA::ISA isa; // one "instance" of the current ISA. public: @@ -230,6 +232,7 @@ class SimpleThread : public ThreadState void clearArchRegs() { regs.clear(); + memset(intRegs, 0, sizeof(intRegs)); memset(floatRegs.i, 0, sizeof(floatRegs.i)); } @@ -239,7 +242,7 @@ class SimpleThread : public ThreadState uint64_t readIntReg(int reg_idx) { int flatIndex = isa.flattenIntIndex(reg_idx); - return regs.readIntReg(flatIndex); + return intRegs[flatIndex]; } FloatReg readFloatReg(int reg_idx) @@ -257,7 +260,7 @@ class SimpleThread : public ThreadState void setIntReg(int reg_idx, uint64_t val) { int flatIndex = isa.flattenIntIndex(reg_idx); - regs.setIntReg(flatIndex, val); + intRegs[flatIndex] = val; } void setFloatReg(int reg_idx, FloatReg val) |