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| author | Gabe Black <gabeblack@google.com> | 2018-03-27 01:24:16 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-03-27 10:58:01 +0000 |
| commit | b18f7078c3e8e9a32294afe107965f28d498f759 (patch) | |
| tree | a685629b8cd49e71a6ff7d5503706843aaa08a6d /src/cpu | |
| parent | 563e19d1fd151fe222af2455536d8239f5c6d3dc (diff) | |
| download | gem5-b18f7078c3e8e9a32294afe107965f28d498f759.tar.xz | |
cpu: Remove ExtMachInst typedefs from the O3 CPU model.
These typedefs aren't used, and they expose ISA specific types outside
the ISA implementations.
Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34
Reviewed-on: https://gem5-review.googlesource.com/9404
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/o3/dyn_inst.hh | 2 | ||||
| -rw-r--r-- | src/cpu/o3/fetch.hh | 1 |
2 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 8a0ae1d56..47dc830e0 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -65,8 +65,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> /** Binary machine instruction type. */ typedef TheISA::MachInst MachInst; - /** Extended machine instruction type. */ - typedef TheISA::ExtMachInst ExtMachInst; /** Register types. */ typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 672fb499b..4382197f4 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -83,7 +83,6 @@ class DefaultFetch /** Typedefs from ISA. */ typedef TheISA::MachInst MachInst; - typedef TheISA::ExtMachInst ExtMachInst; class FetchTranslation : public BaseTLB::Translation { |