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authorGabe Black <gabeblack@google.com>2019-11-04 16:27:34 -0800
committerGabe Black <gabeblack@google.com>2019-11-26 03:01:32 +0000
commit57e951f6eae1de88988a9b13035c07985a0bcd73 (patch)
treee0eebcc48ab14e7106f1a41b09d82f8390357c34 /src/cpu
parent97a6a64f286fb07557843d88776fbc69606b9d88 (diff)
downloadgem5-57e951f6eae1de88988a9b13035c07985a0bcd73.tar.xz
arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.
This conditional compilation was unnecessary and makes gem5 more brittle and harder to understand. Change-Id: I63abaf2668252c988cdd4626ff6a462eb6f54b04 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22544 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/simple_thread.hh27
-rw-r--r--src/cpu/thread_context.cc24
2 files changed, 12 insertions, 39 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 033a0777a..f25e62249 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -109,9 +109,7 @@ class SimpleThread : public ThreadState, public ThreadContext
std::array<RegVal, TheISA::NumIntRegs> intRegs;
std::array<VecRegContainer, TheISA::NumVecRegs> vecRegs;
std::array<VecPredRegContainer, TheISA::NumVecPredRegs> vecPredRegs;
-#ifdef ISA_HAS_CC_REGS
std::array<RegVal, TheISA::NumCCRegs> ccRegs;
-#endif
TheISA::ISA *const isa; // one "instance" of the current ISA.
TheISA::PCState _pcState;
@@ -299,9 +297,7 @@ class SimpleThread : public ThreadState, public ThreadContext
vec_reg.zero();
for (auto &pred_reg: vecPredRegs)
pred_reg.reset();
-#ifdef ISA_HAS_CC_REGS
ccRegs.fill(0);
-#endif
isa->clear();
}
@@ -468,7 +464,6 @@ class SimpleThread : public ThreadState, public ThreadContext
RegVal
readCCReg(RegIndex reg_idx) const override
{
-#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
assert(0 <= flatIndex);
assert(flatIndex < TheISA::NumCCRegs);
@@ -476,10 +471,6 @@ class SimpleThread : public ThreadState, public ThreadContext
DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
reg_idx, flatIndex, regVal);
return regVal;
-#else
- panic("Tried to read a CC register.");
- return 0;
-#endif
}
void
@@ -538,15 +529,11 @@ class SimpleThread : public ThreadState, public ThreadContext
void
setCCReg(RegIndex reg_idx, RegVal val) override
{
-#ifdef ISA_HAS_CC_REGS
int flatIndex = isa->flattenCCIndex(reg_idx);
assert(flatIndex < TheISA::NumCCRegs);
DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
reg_idx, flatIndex, val);
setCCRegFlat(flatIndex, val);
-#else
- panic("Tried to set a CC register.");
-#endif
}
TheISA::PCState pcState() const override { return _pcState; }
@@ -707,22 +694,8 @@ class SimpleThread : public ThreadState, public ThreadContext
vecPredRegs[reg] = val;
}
-#ifdef ISA_HAS_CC_REGS
RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; }
void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; }
-#else
- RegVal
- readCCRegFlat(RegIndex idx) const override
- {
- panic("readCCRegFlat w/no CC regs!\n");
- }
-
- void
- setCCRegFlat(RegIndex idx, RegVal val) override
- {
- panic("setCCRegFlat w/no CC regs!\n");
- }
-#endif
};
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index dea39015f..f8c422c98 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -191,12 +191,12 @@ serialize(const ThreadContext &tc, CheckpointOut &cp)
intRegs[i] = tc.readIntRegFlat(i);
SERIALIZE_ARRAY(intRegs, NumIntRegs);
-#ifdef ISA_HAS_CC_REGS
- RegVal ccRegs[NumCCRegs];
- for (int i = 0; i < NumCCRegs; ++i)
- ccRegs[i] = tc.readCCRegFlat(i);
- SERIALIZE_ARRAY(ccRegs, NumCCRegs);
-#endif
+ if (NumCCRegs) {
+ RegVal ccRegs[NumCCRegs];
+ for (int i = 0; i < NumCCRegs; ++i)
+ ccRegs[i] = tc.readCCRegFlat(i);
+ SERIALIZE_ARRAY(ccRegs, NumCCRegs);
+ }
tc.pcState().serialize(cp);
@@ -232,12 +232,12 @@ unserialize(ThreadContext &tc, CheckpointIn &cp)
for (int i = 0; i < NumIntRegs; ++i)
tc.setIntRegFlat(i, intRegs[i]);
-#ifdef ISA_HAS_CC_REGS
- RegVal ccRegs[NumCCRegs];
- UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
- for (int i = 0; i < NumCCRegs; ++i)
- tc.setCCRegFlat(i, ccRegs[i]);
-#endif
+ if (NumCCRegs) {
+ RegVal ccRegs[NumCCRegs];
+ UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
+ for (int i = 0; i < NumCCRegs; ++i)
+ tc.setCCRegFlat(i, ccRegs[i]);
+ }
PCState pcState;
pcState.unserialize(cp);